This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the transistor-level design of multiple-valued arithmetic circuits. An important feature of EGG is its capability to optimize general graph structures directly instead of encoding the structures into indirect representations, such as bit strings and trees. The potential capability of EGG is demonstrated through an experimental synthesis of a radix-4 signed-digit full adder circuit.
|Number of pages||6|
|Journal||Proceedings of The International Symposium on Multiple-Valued Logic|
|Publication status||Published - 2001|
|Event||31st IEEE International Symposium on Multiple-Valued Logic (ISMVL 2001) - Warsaw, Poland|
Duration: 2001 May 22 → 2001 May 24