TY - JOUR
T1 - Synthesis of multiple-valued arithmetic circuits using evolutionary graph generation
AU - Natsui, M.
AU - Aoki, T.
AU - Higuchi, T.
PY - 2001
Y1 - 2001
N2 - This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the transistor-level design of multiple-valued arithmetic circuits. An important feature of EGG is its capability to optimize general graph structures directly instead of encoding the structures into indirect representations, such as bit strings and trees. The potential capability of EGG is demonstrated through an experimental synthesis of a radix-4 signed-digit full adder circuit.
AB - This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the transistor-level design of multiple-valued arithmetic circuits. An important feature of EGG is its capability to optimize general graph structures directly instead of encoding the structures into indirect representations, such as bit strings and trees. The potential capability of EGG is demonstrated through an experimental synthesis of a radix-4 signed-digit full adder circuit.
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M3 - Conference article
AN - SCOPUS:0034835508
SN - 0195-623X
SP - 253
EP - 258
JO - Proceedings of The International Symposium on Multiple-Valued Logic
JF - Proceedings of The International Symposium on Multiple-Valued Logic
T2 - 31st IEEE International Symposium on Multiple-Valued Logic (ISMVL 2001)
Y2 - 22 May 2001 through 24 May 2001
ER -