TY - GEN
T1 - System for Automatic Generation of Parallel Multipliers over Galois Fields
AU - Sugawara, Yukihiro
AU - Ueno, Rei
AU - Homma, Naofumi
AU - Aoki, Takafumi
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/9/2
Y1 - 2015/9/2
N2 - This paper presents a system for the automatic generation of Galois-field (GF) arithmetic circuits, named the GF Arithmetic Module Generator (GF-AMG). The proposed system employs a graph-based circuit description called the GF Arithmetic Circuit Graph (GF-ACG). First, we present an extension of the GF-ACG to handle GF(pm) (p ≥ 3) arithmetic circuits, which can be efficiently implemented by multiple-valued logic circuits in addition to the conventional binary circuits. We then show the validity of the generation system through the experimental design of GF(3m) multipliers for a ternary logic circuit. In addition, we evaluate the performance of typical GF(2m) multipliers empirically generated by our system. We confirm from the results that the proposed system can generate a variety of GF parallel multipliers, including practical multipliers over GF(2m) and GF(3m) having degrees greater than 128.
AB - This paper presents a system for the automatic generation of Galois-field (GF) arithmetic circuits, named the GF Arithmetic Module Generator (GF-AMG). The proposed system employs a graph-based circuit description called the GF Arithmetic Circuit Graph (GF-ACG). First, we present an extension of the GF-ACG to handle GF(pm) (p ≥ 3) arithmetic circuits, which can be efficiently implemented by multiple-valued logic circuits in addition to the conventional binary circuits. We then show the validity of the generation system through the experimental design of GF(3m) multipliers for a ternary logic circuit. In addition, we evaluate the performance of typical GF(2m) multipliers empirically generated by our system. We confirm from the results that the proposed system can generate a variety of GF parallel multipliers, including practical multipliers over GF(2m) and GF(3m) having degrees greater than 128.
KW - automatic generation
KW - formal design
KW - GF arithmetic circuit
KW - multiple-valued logic
KW - parallel multipliers
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U2 - 10.1109/ISMVL.2015.15
DO - 10.1109/ISMVL.2015.15
M3 - Conference contribution
AN - SCOPUS:84957950657
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 54
EP - 59
BT - Proceedings - 2015 IEEE 45th International Symposium on Multiple-Valued Logic, ISMVL 2015
PB - IEEE Computer Society
T2 - 45th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2015
Y2 - 18 May 2015 through 20 May 2015
ER -