Systematic interpretation of redundant arithmetic adders in binary and multiple-valued logic

Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to describe and analyze addition algorithms at various levels of abstraction. A high-level CTD represents a network of coarse-grained components associated with multiple-valued logic devices, while a low-level CTD represents a network of primitive components directly mapped onto binary logic devices. The level of abstraction in circuit representation can be changed by decomposition of CTDs. We can derive possible variations of adder structures by decomposing a high-level CTD into low-level CTDs. This paper demonstrates the interpretation of redundant arithmetic adders based on CTDs. We first introduce an extension of CTDs to represent possible redundant arithmetic adders with limited carry propagation. Using the extended version of CTDs, we can classify the conventional adder structures including those using emerging devices into three types in a systematic way.

Original languageEnglish
Pages (from-to)1645-1654
Number of pages10
JournalIEICE Transactions on Electronics
Issue number11
Publication statusPublished - 2006 Nov


  • Addition algorithms
  • Arithmetic circuits
  • Datapaths
  • Multiple-valued logic
  • Number systems


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