Temperature compensated piezoresistor fabricated by high energy ion implantation

Takahiro Nishimoto, Shuichi Shoji, Kazuyuki Minami, Masayoshi Esashi

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


We developed piezoresistors with an intrinsic compensation of the offset temperature characteristics. High energy ion implantation was applied to fabricate this type of piezoresistor [1]. The dopant profile of the buried piezoresistor resembles to that of the junction gate field effect transistor (JFET). The buried layer corresponds to a channel of JFET, and the substrate bias corresponds to the gate voltage. Owing to the independent temperature varying parameters, i.e., width of the depletion layer and carrier mobility in the channel, the drain current of the JFET has a temperature independent point at an appropriate gate source voltage. The effect was used in the new type of buried piezoresistor which has a driving point of zero temperature coefficient of resistance at an appropriate gate source voltage.

Original languageEnglish
Pages (from-to)152-156
Number of pages5
JournalIEICE Transactions on Electronics
Issue number2
Publication statusPublished - 1995 Feb 1

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


Dive into the research topics of 'Temperature compensated piezoresistor fabricated by high energy ion implantation'. Together they form a unique fingerprint.

Cite this