The potential of on-chip memory systems for future vector architectures

Hiroaki Kobayashi; Akihiko Musa; Yoshiei Sato; Hiroyuki Takizawa; Koki Okabe

doi:10.1007/978-3-540-74384-2_18

The potential of on-chip memory systems for future vector architectures

Hiroaki Kobayashi, Akihiko Musa, Yoshiei Sato, Hiroyuki Takizawa, Koki Okabe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Citations (Scopus)

Abstract

Summary In this paper, we have discussed the potential of on-chip memory subsystems for future vector architectures. The performance evaluation based on the early experiments suggests that even with moderate-sized on-chip cache with 512KB to 2MB, it covered a lack of the memory bandwidths of vector load/store units with 2B/flop or lower, and boosted the sustained system performance up to the level of the 4B/flop performance. Selective caching, in which only the data with the high locality of reference are cached, is also effective for efficient use of limited on-chip caches.

Original language	English
Title of host publication	High Performance Computing on Vector Systems 2007
Publisher	Springer Science and Business Media, LLC
Pages	247-264
Number of pages	18
ISBN (Print)	9783540743835
DOIs	https://doi.org/10.1007/978-3-540-74384-2_18
Publication status	Published - 2008
Event	2007 7th Teraflop Workshop - Sendai, Japan Duration: 2007 Nov 21 → 2007 Nov 22

Publication series

Name	High Performance Computing on Vector Systems 2007

Conference

Conference	2007 7th Teraflop Workshop
Country/Territory	Japan
City	Sendai
Period	07/11/21 → 07/11/22

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10.1007/978-3-540-74384-2_18

Cite this

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title = "The potential of on-chip memory systems for future vector architectures",

abstract = "Summary In this paper, we have discussed the potential of on-chip memory subsystems for future vector architectures. The performance evaluation based on the early experiments suggests that even with moderate-sized on-chip cache with 512KB to 2MB, it covered a lack of the memory bandwidths of vector load/store units with 2B/flop or lower, and boosted the sustained system performance up to the level of the 4B/flop performance. Selective caching, in which only the data with the high locality of reference are cached, is also effective for efficient use of limited on-chip caches.",

author = "Hiroaki Kobayashi and Akihiko Musa and Yoshiei Sato and Hiroyuki Takizawa and Koki Okabe",

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Kobayashi, H, Musa, A, Sato, Y, Takizawa, H & Okabe, K 2008, The potential of on-chip memory systems for future vector architectures. in High Performance Computing on Vector Systems 2007. High Performance Computing on Vector Systems 2007, Springer Science and Business Media, LLC, pp. 247-264, 2007 7th Teraflop Workshop, Sendai, Japan, 07/11/21. https://doi.org/10.1007/978-3-540-74384-2_18

The potential of on-chip memory systems for future vector architectures. / Kobayashi, Hiroaki; Musa, Akihiko; Sato, Yoshiei et al.
High Performance Computing on Vector Systems 2007. Springer Science and Business Media, LLC, 2008. p. 247-264 (High Performance Computing on Vector Systems 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Summary In this paper, we have discussed the potential of on-chip memory subsystems for future vector architectures. The performance evaluation based on the early experiments suggests that even with moderate-sized on-chip cache with 512KB to 2MB, it covered a lack of the memory bandwidths of vector load/store units with 2B/flop or lower, and boosted the sustained system performance up to the level of the 4B/flop performance. Selective caching, in which only the data with the high locality of reference are cached, is also effective for efficient use of limited on-chip caches.

AB - Summary In this paper, we have discussed the potential of on-chip memory subsystems for future vector architectures. The performance evaluation based on the early experiments suggests that even with moderate-sized on-chip cache with 512KB to 2MB, it covered a lack of the memory bandwidths of vector load/store units with 2B/flop or lower, and boosted the sustained system performance up to the level of the 4B/flop performance. Selective caching, in which only the data with the high locality of reference are cached, is also effective for efficient use of limited on-chip caches.

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The potential of on-chip memory systems for future vector architectures

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