TY - GEN
T1 - Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories
AU - Liu, Chia Yin
AU - Chen, Yi Jung
AU - Hariyama, Masanori
N1 - Funding Information:
This work was supported in part by research grants from the Ministry of Science and Technology of Taiwan (MOST-108-2918-I-260-005-, MOST-107-2221-E-260-004-MY2, MOST-106-2221-E-260-022-, and MOST-105-2221-E-260-024-).
Publisher Copyright:
© 2020 ACM.
PY - 2020/3/30
Y1 - 2020/3/30
N2 - Integrating Multi-Processor System-on-Chips (MPSoCs) and memories vertically by Through-Silicon Vias (TSVs) provides abundant memory bandwidth, but the increase of power density also makes the system frequently work under thermal emergent states. Although several thermal-aware TSV placement methods have been proposed to ease the thermal issue from the architectural design points of view, the overlooking of designing the type of stacked memories and memory interface in synergy may lead to thermal inefficient designs. The stacked memories may be SRAMs, DRAMs, or even NVMs, and they are divergent in power, performance, and thermal behavior, which in turn would greatly affect the memory interface design, i.e. TSV placements. In this paper, we propose the first thermal-aware memory system synthesis method for MPSoCs with 3D-stacked hybrid memories. The proposed method synergistically synthesizes the type of stacked memories and the memory interface aiming at optimizing performance while the thermal constraint is met. The results show that, among all the tested cases, the proposed method successfully keep peak temperature under 85°C with at most 29% of performance degradation.
AB - Integrating Multi-Processor System-on-Chips (MPSoCs) and memories vertically by Through-Silicon Vias (TSVs) provides abundant memory bandwidth, but the increase of power density also makes the system frequently work under thermal emergent states. Although several thermal-aware TSV placement methods have been proposed to ease the thermal issue from the architectural design points of view, the overlooking of designing the type of stacked memories and memory interface in synergy may lead to thermal inefficient designs. The stacked memories may be SRAMs, DRAMs, or even NVMs, and they are divergent in power, performance, and thermal behavior, which in turn would greatly affect the memory interface design, i.e. TSV placements. In this paper, we propose the first thermal-aware memory system synthesis method for MPSoCs with 3D-stacked hybrid memories. The proposed method synergistically synthesizes the type of stacked memories and the memory interface aiming at optimizing performance while the thermal constraint is met. The results show that, among all the tested cases, the proposed method successfully keep peak temperature under 85°C with at most 29% of performance degradation.
KW - 3D-stacked hybrid memories
KW - MPSoCs
KW - System-level synthesis
KW - Thermal efficiency
KW - Thermal-aware design
UR - http://www.scopus.com/inward/record.url?scp=85083035462&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85083035462&partnerID=8YFLogxK
U2 - 10.1145/3341105.3373858
DO - 10.1145/3341105.3373858
M3 - Conference contribution
AN - SCOPUS:85083035462
T3 - Proceedings of the ACM Symposium on Applied Computing
SP - 546
EP - 553
BT - 35th Annual ACM Symposium on Applied Computing, SAC 2020
PB - Association for Computing Machinery
T2 - 35th Annual ACM Symposium on Applied Computing, SAC 2020
Y2 - 30 March 2020 through 3 April 2020
ER -