Thermal Stress in Silicon Chips Encapsulated in IC Plastic Packages

Hideo Miura, Asao Nishimura, Sueo Kawai, Kunihiko Nishi

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


Thermal stress in silicon chips encapsulated in IC plastic packages was discussed using stress-sensing chips which the authors developed utilizing the piezoresistive effect of silicon. Sensor chips were encapsulated in dual-in-line-type packages using various combinations of packaging materials: metallic leadframe, die-bonding paste, and resin. Thermal stress in the silicon chip was measured with changing oven temperature between 20°C and 100°C. It was found that thermal stress in silicon chips changes almost linearly with temperature. The stress varied with the material combination of the package from 75 MPa to 110 MPa when the temperature decreased from 100°C to 20°C. However, the thermal stress varied irreversibly with temperature when epoxy paste was used as the die-bonding paste. This unstable stress change with temperature was due to propagation of the delamination between a silicon chip and metallic leadframe.

Original languageEnglish
Pages (from-to)1575-1580
Number of pages6
JournalNihon Kikai Gakkai Ronbunshu, A Hen/Transactions of the Japan Society of Mechanical Engineers, Part A
Issue number539
Publication statusPublished - 1991


  • Experimental Stress Analysis
  • IC Plastic Package
  • Piezoresistive Effect
  • Structural Reliability
  • Thermal Stress Delamination
  • Ultrasonic Inspection


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