Three-dimensional integration of fully depleted silicon-on-insulator transistor substrates for CMOS image sensors using Au/SiO₂ hybrid bonding and XeF₂ etching

We have investigated a pixel-parallel signal processing CMOS image sensor for future TV broadcast equipment. The device has a three-dimensional structure containing functional layers made up of components such as photodiodes and signal processors formed on fully depleted silicon-on-insulator transistor substrates connected with vertical interconnections formed for each pixel. To demonstrate the effectiveness of this approach, a test chip is experimentally constructed using Au/SiO₂ hybrid bonding technology. Mechanical grinding and XeF₂ etching are utilized to remove the backside Si layer to allow light transmission to the photodiode. Due to the high bonding strength after the surface activation treatment, the Si layer thickness could be reduced to 40 μm without chipping. The proposed approach is highly promising for the fabrication of three-dimensional integrated image sensors.