Three-dimensional integration technology and integrated systems

Mitsumasa Koyanagi; Takafumi Fukushima; Tetsu Tanaka

doi:10.1109/ASPDAC.2009.4796515

Three-dimensional integration technology and integrated systems

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

33 Citations (Scopus)

Abstract

A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2009
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2009
Pages	409-415
Number of pages	7
DOIs	https://doi.org/10.1109/ASPDAC.2009.4796515
Publication status	Published - 2009
Event	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan Duration: 2009 Jan 19 → 2009 Jan 22

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
Country/Territory	Japan
City	Yokohama
Period	09/1/19 → 09/1/22

Access to Document

10.1109/ASPDAC.2009.4796515

Cite this

@inproceedings{44b745d2b17141ceab30b32a181c3850,

title = "Three-dimensional integration technology and integrated systems",

abstract = "A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration.",

author = "Mitsumasa Koyanagi and Takafumi Fukushima and Tetsu Tanaka",

year = "2009",

doi = "10.1109/ASPDAC.2009.4796515",

language = "English",

isbn = "9781424427482",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "409--415",

booktitle = "Proceedings of the ASP-DAC 2009",

note = "Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 ; Conference date: 19-01-2009 Through 22-01-2009",

}

Koyanagi, M, Fukushima, T & Tanaka, T 2009, Three-dimensional integration technology and integrated systems. in Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009., 4796515, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 409-415, Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009, Yokohama, Japan, 09/1/19. https://doi.org/10.1109/ASPDAC.2009.4796515

Three-dimensional integration technology and integrated systems. / Koyanagi, Mitsumasa; Fukushima, Takafumi ; Tanaka, Tetsu.
Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009. 2009. p. 409-415 4796515 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Three-dimensional integration technology and integrated systems

AU - Koyanagi, Mitsumasa

AU - Fukushima, Takafumi

AU - Tanaka, Tetsu

PY - 2009

Y1 - 2009

N2 - A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration.

AB - A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration.

UR - http://www.scopus.com/inward/record.url?scp=64549097598&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=64549097598&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2009.4796515

DO - 10.1109/ASPDAC.2009.4796515

M3 - Conference contribution

AN - SCOPUS:64549097598

SN - 9781424427482

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 409

EP - 415

BT - Proceedings of the ASP-DAC 2009

T2 - Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009

Y2 - 19 January 2009 through 22 January 2009

ER -

Three-dimensional integration technology and integrated systems

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