Three-dimensional integration technology based on self-assembled chip-to-wafer stacking

Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


We have demonstrated that a number of known good dies (KGDs) can be precisely aligned in batch and stacked on LSI wafers by our chip-to-wafer three-dimensional (3D) integration technology using an innovative self-assembly technique. Compared with conventional robotic pick-and-place chip assembly, the fluidic self-assembly can provide high-throughput chip alignment and bonding, and the resulting self-assembled chips have high alignment accuracy of approximately 0.3 μm on average. Immediately after chip release, the chips are aligned onto the predetermined hydrophilic bonding areas in a short time within 0.1 sec by the surface tension of aqueous liquid used in our self-assembly. By using the self-assembly, a number of KGDs with different chip sizes, different materials and different devices can be stacked in high yield to give highly integrated 3D chips we call the 3D Super Chip.

Original languageEnglish
Title of host publicationMaterials Research Society Symposium Proceedings - Materials and Technologies for 3-D Integration
Number of pages10
Publication statusPublished - 2009
EventMaterials and Technologies for 3-D Integration - 2008 MRS Fall Meeting - Boston, MA, United States
Duration: 2008 Dec 12008 Dec 3

Publication series

NameMaterials Research Society Symposium Proceedings
ISSN (Print)0272-9172


ConferenceMaterials and Technologies for 3-D Integration - 2008 MRS Fall Meeting
Country/TerritoryUnited States
CityBoston, MA


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