Three-dimensional integration technology using self-assembly technique and super-chip integration

Mitsumasa Koyanagi; Takafumi Fukushima; Tetsu Tanaka

doi:10.1109/IITC.2008.4546910

Three-dimensional integration technology using self-assembly technique and super-chip integration

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

We have proposed a new three-dimensional (3-D) integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5μm. We have fabricated 3-D LSI test chips by a super-chip integration technology.

Original language	English
Title of host publication	2008 IEEE International Interconnect Technology Conference, IITC
Pages	10-12
Number of pages	3
DOIs	https://doi.org/10.1109/IITC.2008.4546910
Publication status	Published - 2008
Event	2008 IEEE International Interconnect Technology Conference, IITC - Burlingame, CA, United States Duration: 2008 Jun 1 → 2008 Jun 4

Publication series

Name	2008 IEEE International Interconnect Technology Conference, IITC

Conference

Conference	2008 IEEE International Interconnect Technology Conference, IITC
Country/Territory	United States
City	Burlingame, CA
Period	08/6/1 → 08/6/4

Keywords

Chip-to-wafer bonding
Self-assembly
Super-chip
Three-dimensional (3-D) LSI
Through-silicon-via (TSV)

Access to Document

10.1109/IITC.2008.4546910

Cite this

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title = "Three-dimensional integration technology using self-assembly technique and super-chip integration",

abstract = "We have proposed a new three-dimensional (3-D) integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5μm. We have fabricated 3-D LSI test chips by a super-chip integration technology.",

keywords = "Chip-to-wafer bonding, Self-assembly, Super-chip, Three-dimensional (3-D) LSI, Through-silicon-via (TSV)",

author = "Mitsumasa Koyanagi and Takafumi Fukushima and Tetsu Tanaka",

year = "2008",

doi = "10.1109/IITC.2008.4546910",

language = "English",

isbn = "9781424419111",

series = "2008 IEEE International Interconnect Technology Conference, IITC",

pages = "10--12",

booktitle = "2008 IEEE International Interconnect Technology Conference, IITC",

note = "2008 IEEE International Interconnect Technology Conference, IITC ; Conference date: 01-06-2008 Through 04-06-2008",

}

Koyanagi, M, Fukushima, T & Tanaka, T 2008, Three-dimensional integration technology using self-assembly technique and super-chip integration. in 2008 IEEE International Interconnect Technology Conference, IITC., 4546910, 2008 IEEE International Interconnect Technology Conference, IITC, pp. 10-12, 2008 IEEE International Interconnect Technology Conference, IITC, Burlingame, CA, United States, 08/6/1. https://doi.org/10.1109/IITC.2008.4546910

Three-dimensional integration technology using self-assembly technique and super-chip integration. / Koyanagi, Mitsumasa; Fukushima, Takafumi ; Tanaka, Tetsu.
2008 IEEE International Interconnect Technology Conference, IITC. 2008. p. 10-12 4546910 (2008 IEEE International Interconnect Technology Conference, IITC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Three-dimensional integration technology using self-assembly technique and super-chip integration

AU - Koyanagi, Mitsumasa

AU - Fukushima, Takafumi

AU - Tanaka, Tetsu

PY - 2008

Y1 - 2008

N2 - We have proposed a new three-dimensional (3-D) integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5μm. We have fabricated 3-D LSI test chips by a super-chip integration technology.

AB - We have proposed a new three-dimensional (3-D) integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5μm. We have fabricated 3-D LSI test chips by a super-chip integration technology.

KW - Chip-to-wafer bonding

KW - Self-assembly

KW - Super-chip

KW - Three-dimensional (3-D) LSI

KW - Through-silicon-via (TSV)

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BT - 2008 IEEE International Interconnect Technology Conference, IITC

T2 - 2008 IEEE International Interconnect Technology Conference, IITC

Y2 - 1 June 2008 through 4 June 2008

ER -

Three-dimensional integration technology using self-assembly technique and super-chip integration

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Keywords

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