TiN/W/La2O3/Si high-k gate stack for EOT below 0.5nm

P. Ahmet; D. Kitayama; T. Kaneda; T. Suzuki; T. Koyanagi; M. Kouda; M. Mamatrishat; T. Kawanago; K. Kakushima; K. Tsutsui; A. Nishiyama; N. Sugii; K. Natori; T. Hattori; H. Iwai

doi:10.1149/1.3567566

TiN/W/La₂O₃/Si high-k gate stack for EOT below 0.5nm

P. Ahmet, D. Kitayama, T. Kaneda, T. Suzuki, T. Koyanagi, M. Kouda, M. Mamatrishat, T. Kawanago, K. Kakushima, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Electrical properties of TiN/W/La₂O₃ high-k gate stack were studied by fabricating MOS capacitors. Obtained results showed that a W layer inserted at the interface between TiN and La₂O₃ is the key factor in suppression of the equivalent oxide thickness (EOT) increment during the annealing process. An EOT of 0.43nm was achieved with a 3nm W inserted layer after annealed at 800°C in a forming gas ambient. Our results show that TiN/W/La₂O₃ gate stack is one of the promising candidates for realizing high-k gate stack with EOT of 0.5nm and beyond.

Original language	English
Title of host publication	China Semiconductor Technology International Conference 2011, CSTIC 2011
Pages	99-102
Number of pages	4
Edition	1
DOIs	https://doi.org/10.1149/1.3567566
Publication status	Published - 2011
Externally published	Yes
Event	10th China Semiconductor Technology International Conference 2011, CSTIC 2011 - Shanghai, China Duration: 2011 Mar 13 → 2011 Mar 14

Publication series

Name	ECS Transactions
Number	1
Volume	34
ISSN (Print)	1938-5862
ISSN (Electronic)	1938-6737

Other

Other	10th China Semiconductor Technology International Conference 2011, CSTIC 2011
Country/Territory	China
City	Shanghai
Period	11/3/13 → 11/3/14

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1149/1.3567566

Cite this

Ahmet, P., Kitayama, D., Kaneda, T., Suzuki, T., Koyanagi, T., Kouda, M., Mamatrishat, M., Kawanago, T., Kakushima, K., Tsutsui, K., Nishiyama, A., Sugii, N., Natori, K., Hattori, T., & Iwai, H. (2011). TiN/W/La₂O₃/Si high-k gate stack for EOT below 0.5nm. In China Semiconductor Technology International Conference 2011, CSTIC 2011 (1 ed., pp. 99-102). (ECS Transactions; Vol. 34, No. 1). https://doi.org/10.1149/1.3567566

Ahmet, P, Kitayama, D, Kaneda, T, Suzuki, T, Koyanagi, T, Kouda, M, Mamatrishat, M, Kawanago, T, Kakushima, K, Tsutsui, K, Nishiyama, A, Sugii, N, Natori, K, Hattori, T & Iwai, H 2011, TiN/W/La₂O₃/Si high-k gate stack for EOT below 0.5nm. in China Semiconductor Technology International Conference 2011, CSTIC 2011. 1 edn, ECS Transactions, no. 1, vol. 34, pp. 99-102, 10th China Semiconductor Technology International Conference 2011, CSTIC 2011, Shanghai, China, 11/3/13. https://doi.org/10.1149/1.3567566

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title = "TiN/W/La2O3/Si high-k gate stack for EOT below 0.5nm",

abstract = "Electrical properties of TiN/W/La2O3 high-k gate stack were studied by fabricating MOS capacitors. Obtained results showed that a W layer inserted at the interface between TiN and La2O3 is the key factor in suppression of the equivalent oxide thickness (EOT) increment during the annealing process. An EOT of 0.43nm was achieved with a 3nm W inserted layer after annealed at 800°C in a forming gas ambient. Our results show that TiN/W/La2O3 gate stack is one of the promising candidates for realizing high-k gate stack with EOT of 0.5nm and beyond.",

author = "P. Ahmet and D. Kitayama and T. Kaneda and T. Suzuki and T. Koyanagi and M. Kouda and M. Mamatrishat and T. Kawanago and K. Kakushima and K. Tsutsui and A. Nishiyama and N. Sugii and K. Natori and T. Hattori and H. Iwai",

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T1 - TiN/W/La2O3/Si high-k gate stack for EOT below 0.5nm

AU - Ahmet, P.

AU - Kitayama, D.

AU - Kaneda, T.

AU - Suzuki, T.

AU - Koyanagi, T.

AU - Kouda, M.

AU - Mamatrishat, M.

AU - Kawanago, T.

AU - Kakushima, K.

AU - Tsutsui, K.

AU - Nishiyama, A.

AU - Sugii, N.

AU - Natori, K.

AU - Hattori, T.

AU - Iwai, H.

PY - 2011

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N2 - Electrical properties of TiN/W/La2O3 high-k gate stack were studied by fabricating MOS capacitors. Obtained results showed that a W layer inserted at the interface between TiN and La2O3 is the key factor in suppression of the equivalent oxide thickness (EOT) increment during the annealing process. An EOT of 0.43nm was achieved with a 3nm W inserted layer after annealed at 800°C in a forming gas ambient. Our results show that TiN/W/La2O3 gate stack is one of the promising candidates for realizing high-k gate stack with EOT of 0.5nm and beyond.

AB - Electrical properties of TiN/W/La2O3 high-k gate stack were studied by fabricating MOS capacitors. Obtained results showed that a W layer inserted at the interface between TiN and La2O3 is the key factor in suppression of the equivalent oxide thickness (EOT) increment during the annealing process. An EOT of 0.43nm was achieved with a 3nm W inserted layer after annealed at 800°C in a forming gas ambient. Our results show that TiN/W/La2O3 gate stack is one of the promising candidates for realizing high-k gate stack with EOT of 0.5nm and beyond.

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