TMR design methodology for SPin-transfer torque RAM (SPRAM) with nonvolatile and SRAM compatible operations

R. Takemura; T. Kawahara; J. Hayakawa; K. Miura; K. Ito; M. Yamanouchi; S. Ikeda; H. Takahashi; H. Matsuoka; H. Ohno

doi:10.1109/NVSMW.2008.22

TMR design methodology for SPin-transfer torque RAM (SPRAM) with nonvolatile and SRAM compatible operations

R. Takemura, T. Kawahara, J. Hayakawa, K. Miura, K. Ito, M. Yamanouchi, S. Ikeda, H. Takahashi, H. Matsuoka, H. Ohno

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Citations (Scopus)

Abstract

We propose a tunnel magneto resistance (TMR) design methodology for SPRAM that takes into account the disturbances during read operations and the data retention periods. We have clarified that the thermal stability factor (E/k _BT) of TMR must be higher than 64 to ensure a 10-year data retention and a continual non-destructive read-operation. Moreover, the thick synthetic ferromagnetic free layer with Fe-rich CoFeB can achieve a E/k_BT of 64 while maintaining a low write cell current of less than 400 μA/cell with a 100 x 160 nm² TMR.

Original language	English
Title of host publication	2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD
Pages	54-55
Number of pages	2
DOIs	https://doi.org/10.1109/NVSMW.2008.22
Publication status	Published - 2008
Event	2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, NVSMW/ICMTD - Opio, France Duration: 2008 May 18 → 2008 May 22

Publication series

Name	2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD

Conference

Conference	2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, NVSMW/ICMTD
Country/Territory	France
City	Opio
Period	08/5/18 → 08/5/22

Access to Document

10.1109/NVSMW.2008.22

Cite this

Takemura, R., Kawahara, T., Hayakawa, J., Miura, K., Ito, K., Yamanouchi, M., Ikeda, S., Takahashi, H., Matsuoka, H., & Ohno, H. (2008). TMR design methodology for SPin-transfer torque RAM (SPRAM) with nonvolatile and SRAM compatible operations. In 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD (pp. 54-55). Article 4531822 (2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD). https://doi.org/10.1109/NVSMW.2008.22

Takemura, R. ; Kawahara, T. ; Hayakawa, J. et al. / TMR design methodology for SPin-transfer torque RAM (SPRAM) with nonvolatile and SRAM compatible operations. 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD. 2008. pp. 54-55 (2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD).

@inproceedings{6c35186ecb2f4afa9b72f0f5f5e1e11e,

title = "TMR design methodology for SPin-transfer torque RAM (SPRAM) with nonvolatile and SRAM compatible operations",

abstract = "We propose a tunnel magneto resistance (TMR) design methodology for SPRAM that takes into account the disturbances during read operations and the data retention periods. We have clarified that the thermal stability factor (E/k BT) of TMR must be higher than 64 to ensure a 10-year data retention and a continual non-destructive read-operation. Moreover, the thick synthetic ferromagnetic free layer with Fe-rich CoFeB can achieve a E/kBT of 64 while maintaining a low write cell current of less than 400 μA/cell with a 100 x 160 nm2 TMR.",

author = "R. Takemura and T. Kawahara and J. Hayakawa and K. Miura and K. Ito and M. Yamanouchi and S. Ikeda and H. Takahashi and H. Matsuoka and H. Ohno",

year = "2008",

doi = "10.1109/NVSMW.2008.22",

language = "English",

isbn = "1424415462",

series = "2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD",

pages = "54--55",

booktitle = "2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD",

note = "2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, NVSMW/ICMTD ; Conference date: 18-05-2008 Through 22-05-2008",

}

Takemura, R, Kawahara, T, Hayakawa, J, Miura, K, Ito, K, Yamanouchi, M, Ikeda, S, Takahashi, H, Matsuoka, H & Ohno, H 2008, TMR design methodology for SPin-transfer torque RAM (SPRAM) with nonvolatile and SRAM compatible operations. in 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD., 4531822, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD, pp. 54-55, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, NVSMW/ICMTD, Opio, France, 08/5/18. https://doi.org/10.1109/NVSMW.2008.22

TMR design methodology for SPin-transfer torque RAM (SPRAM) with nonvolatile and SRAM compatible operations. / Takemura, R.; Kawahara, T.; Hayakawa, J. et al.
2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD. 2008. p. 54-55 4531822 (2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - TMR design methodology for SPin-transfer torque RAM (SPRAM) with nonvolatile and SRAM compatible operations

AU - Takemura, R.

AU - Kawahara, T.

AU - Hayakawa, J.

AU - Miura, K.

AU - Ito, K.

AU - Yamanouchi, M.

AU - Ikeda, S.

AU - Takahashi, H.

AU - Matsuoka, H.

AU - Ohno, H.

PY - 2008

Y1 - 2008

N2 - We propose a tunnel magneto resistance (TMR) design methodology for SPRAM that takes into account the disturbances during read operations and the data retention periods. We have clarified that the thermal stability factor (E/k BT) of TMR must be higher than 64 to ensure a 10-year data retention and a continual non-destructive read-operation. Moreover, the thick synthetic ferromagnetic free layer with Fe-rich CoFeB can achieve a E/kBT of 64 while maintaining a low write cell current of less than 400 μA/cell with a 100 x 160 nm2 TMR.

AB - We propose a tunnel magneto resistance (TMR) design methodology for SPRAM that takes into account the disturbances during read operations and the data retention periods. We have clarified that the thermal stability factor (E/k BT) of TMR must be higher than 64 to ensure a 10-year data retention and a continual non-destructive read-operation. Moreover, the thick synthetic ferromagnetic free layer with Fe-rich CoFeB can achieve a E/kBT of 64 while maintaining a low write cell current of less than 400 μA/cell with a 100 x 160 nm2 TMR.

UR - http://www.scopus.com/inward/record.url?scp=50249168850&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50249168850&partnerID=8YFLogxK

U2 - 10.1109/NVSMW.2008.22

DO - 10.1109/NVSMW.2008.22

M3 - Conference contribution

AN - SCOPUS:50249168850

SN - 1424415462

SN - 9781424415465

T3 - 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD

SP - 54

EP - 55

BT - 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD

T2 - 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, NVSMW/ICMTD

Y2 - 18 May 2008 through 22 May 2008

ER -

Takemura R, Kawahara T, Hayakawa J, Miura K, Ito K, Yamanouchi M et al. TMR design methodology for SPin-transfer torque RAM (SPRAM) with nonvolatile and SRAM compatible operations. In 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD. 2008. p. 54-55. 4531822. (2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings, NVSMW/ICMTD). doi: 10.1109/NVSMW.2008.22

TMR design methodology for SPin-transfer torque RAM (SPRAM) with nonvolatile and SRAM compatible operations

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this