Non-Transfer and transfer based 3D integration technologies are developed to achieve high-Throughput and high-precision multichip-To-wafer stacking. Both the stacking approaches employ KGD self-Assembly technologies using liquid surface tension. In the former stacking scheme, a large number of chips having CMP-Treated plasma-TEOS SiO2 on their top surface are directly self-Assembled in a face-down configuration on an interposer wafer. On the other hand, in the latter stacking scheme, the many chips having the plasma-TEOS SiO2 are self-Assembled in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier, with bipolar electrodes for electrostatic adhesion. The latter chips are transferred from the carrier to another interposer in wafer-level processing. From the point of view of alignment accuracies and direct bonding strengths, the two stacking approaches are compared.