Transfer and Non-Transfer 3D Stacking Technologies Based on Multichip-To-Wafer Self-Assembly and Direct Bonding

T. Fukushima; H. Hashiguchi; H. Kino; T. Tanaka; M. Murugesan; J. Bea; H. Hashimoto; K. Lee; M. Koyanagi

doi:10.1109/ECTC.2016.298

Transfer and Non-Transfer 3D Stacking Technologies Based on Multichip-To-Wafer Self-Assembly and Direct Bonding

T. Fukushima, H. Hashiguchi, H. Kino, T. Tanaka, M. Murugesan, J. Bea, H. Hashimoto, K. Lee, M. Koyanagi

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Citations (Scopus)

Abstract

Non-Transfer and transfer based 3D integration technologies are developed to achieve high-Throughput and high-precision multichip-To-wafer stacking. Both the stacking approaches employ KGD self-Assembly technologies using liquid surface tension. In the former stacking scheme, a large number of chips having CMP-Treated plasma-TEOS SiO2 on their top surface are directly self-Assembled in a face-down configuration on an interposer wafer. On the other hand, in the latter stacking scheme, the many chips having the plasma-TEOS SiO2 are self-Assembled in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier, with bipolar electrodes for electrostatic adhesion. The latter chips are transferred from the carrier to another interposer in wafer-level processing. From the point of view of alignment accuracies and direct bonding strengths, the two stacking approaches are compared.

Original language	English
Title of host publication	Proceedings - ECTC 2016
Subtitle of host publication	66th Electronic Components and Technology Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	289-294
Number of pages	6
ISBN (Electronic)	9781509012039
DOIs	https://doi.org/10.1109/ECTC.2016.298
Publication status	Published - 2016 Aug 16
Event	66th IEEE Electronic Components and Technology Conference, ECTC 2016 - Las Vegas, United States Duration: 2016 May 31 → 2016 Jun 3

Publication series

Name	Proceedings - Electronic Components and Technology Conference
Volume	2016-August
ISSN (Print)	0569-5503

Conference

Conference	66th IEEE Electronic Components and Technology Conference, ECTC 2016
Country/Territory	United States
City	Las Vegas
Period	16/5/31 → 16/6/3

Keywords

3D integration
Multichip-To-wafer stacking
Oxide-oxide direct bonding
Self-Assembly

Access to Document

10.1109/ECTC.2016.298

Cite this

Fukushima, T., Hashiguchi, H., Kino, H., Tanaka, T., Murugesan, M., Bea, J., Hashimoto, H., Lee, K., & Koyanagi, M. (2016). Transfer and Non-Transfer 3D Stacking Technologies Based on Multichip-To-Wafer Self-Assembly and Direct Bonding. In Proceedings - ECTC 2016: 66th Electronic Components and Technology Conference (pp. 289-294). Article 7545446 (Proceedings - Electronic Components and Technology Conference; Vol. 2016-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ECTC.2016.298

Fukushima, T. ; Hashiguchi, H. ; Kino, H. et al. / Transfer and Non-Transfer 3D Stacking Technologies Based on Multichip-To-Wafer Self-Assembly and Direct Bonding. Proceedings - ECTC 2016: 66th Electronic Components and Technology Conference. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 289-294 (Proceedings - Electronic Components and Technology Conference).

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title = "Transfer and Non-Transfer 3D Stacking Technologies Based on Multichip-To-Wafer Self-Assembly and Direct Bonding",

abstract = "Non-Transfer and transfer based 3D integration technologies are developed to achieve high-Throughput and high-precision multichip-To-wafer stacking. Both the stacking approaches employ KGD self-Assembly technologies using liquid surface tension. In the former stacking scheme, a large number of chips having CMP-Treated plasma-TEOS SiO2 on their top surface are directly self-Assembled in a face-down configuration on an interposer wafer. On the other hand, in the latter stacking scheme, the many chips having the plasma-TEOS SiO2 are self-Assembled in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier, with bipolar electrodes for electrostatic adhesion. The latter chips are transferred from the carrier to another interposer in wafer-level processing. From the point of view of alignment accuracies and direct bonding strengths, the two stacking approaches are compared.",

keywords = "3D integration, Multichip-To-wafer stacking, Oxide-oxide direct bonding, Self-Assembly",

author = "T. Fukushima and H. Hashiguchi and H. Kino and T. Tanaka and M. Murugesan and J. Bea and H. Hashimoto and K. Lee and M. Koyanagi",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 66th IEEE Electronic Components and Technology Conference, ECTC 2016 ; Conference date: 31-05-2016 Through 03-06-2016",

year = "2016",

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doi = "10.1109/ECTC.2016.298",

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Fukushima, T, Hashiguchi, H, Kino, H , Tanaka, T, Murugesan, M, Bea, J, Hashimoto, H, Lee, K & Koyanagi, M 2016, Transfer and Non-Transfer 3D Stacking Technologies Based on Multichip-To-Wafer Self-Assembly and Direct Bonding. in Proceedings - ECTC 2016: 66th Electronic Components and Technology Conference., 7545446, Proceedings - Electronic Components and Technology Conference, vol. 2016-August, Institute of Electrical and Electronics Engineers Inc., pp. 289-294, 66th IEEE Electronic Components and Technology Conference, ECTC 2016, Las Vegas, United States, 16/5/31. https://doi.org/10.1109/ECTC.2016.298

Transfer and Non-Transfer 3D Stacking Technologies Based on Multichip-To-Wafer Self-Assembly and Direct Bonding. / Fukushima, T.; Hashiguchi, H.; Kino, H. et al.
Proceedings - ECTC 2016: 66th Electronic Components and Technology Conference. Institute of Electrical and Electronics Engineers Inc., 2016. p. 289-294 7545446 (Proceedings - Electronic Components and Technology Conference; Vol. 2016-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Transfer and Non-Transfer 3D Stacking Technologies Based on Multichip-To-Wafer Self-Assembly and Direct Bonding

AU - Fukushima, T.

AU - Hashiguchi, H.

AU - Kino, H.

AU - Tanaka, T.

AU - Murugesan, M.

AU - Bea, J.

AU - Hashimoto, H.

AU - Lee, K.

AU - Koyanagi, M.

PY - 2016/8/16

Y1 - 2016/8/16

N2 - Non-Transfer and transfer based 3D integration technologies are developed to achieve high-Throughput and high-precision multichip-To-wafer stacking. Both the stacking approaches employ KGD self-Assembly technologies using liquid surface tension. In the former stacking scheme, a large number of chips having CMP-Treated plasma-TEOS SiO2 on their top surface are directly self-Assembled in a face-down configuration on an interposer wafer. On the other hand, in the latter stacking scheme, the many chips having the plasma-TEOS SiO2 are self-Assembled in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier, with bipolar electrodes for electrostatic adhesion. The latter chips are transferred from the carrier to another interposer in wafer-level processing. From the point of view of alignment accuracies and direct bonding strengths, the two stacking approaches are compared.

AB - Non-Transfer and transfer based 3D integration technologies are developed to achieve high-Throughput and high-precision multichip-To-wafer stacking. Both the stacking approaches employ KGD self-Assembly technologies using liquid surface tension. In the former stacking scheme, a large number of chips having CMP-Treated plasma-TEOS SiO2 on their top surface are directly self-Assembled in a face-down configuration on an interposer wafer. On the other hand, in the latter stacking scheme, the many chips having the plasma-TEOS SiO2 are self-Assembled in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier, with bipolar electrodes for electrostatic adhesion. The latter chips are transferred from the carrier to another interposer in wafer-level processing. From the point of view of alignment accuracies and direct bonding strengths, the two stacking approaches are compared.

KW - 3D integration

KW - Multichip-To-wafer stacking

KW - Oxide-oxide direct bonding

KW - Self-Assembly

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BT - Proceedings - ECTC 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 66th IEEE Electronic Components and Technology Conference, ECTC 2016

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ER -

Fukushima T, Hashiguchi H, Kino H , Tanaka T, Murugesan M, Bea J et al. Transfer and Non-Transfer 3D Stacking Technologies Based on Multichip-To-Wafer Self-Assembly and Direct Bonding. In Proceedings - ECTC 2016: 66th Electronic Components and Technology Conference. Institute of Electrical and Electronics Engineers Inc. 2016. p. 289-294. 7545446. (Proceedings - Electronic Components and Technology Conference). doi: 10.1109/ECTC.2016.298

Transfer and Non-Transfer 3D Stacking Technologies Based on Multichip-To-Wafer Self-Assembly and Direct Bonding

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Keywords

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