TY - JOUR
T1 - Transistor on capacitor (TOC) cell with quarter pitch layout for 0.13 μm DRAMs and beyond
AU - Sato, M.
AU - Ishibashi, S.
AU - Kajiyama, T.
AU - Sakuma, M.
AU - Mizushima, I.
AU - Tsunashima, Y.
AU - Shoji, F.
AU - Yano, H.
AU - Nitayama, A.
AU - Hamamoto, T.
N1 - Copyright:
Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.
PY - 2000
Y1 - 2000
N2 - We present a new trench type cell, transistor on capacitor (TOC) cell with 1/4 pitch layout. Two kinds of new idea have been implemented. One is that the density of the trench capacitor is closest packed by introducing 1/4 pitch layout. The other is that the transfer transistor is fabricated over the trench capacitor by introducing the newly developed epitaxial growth and Chemical Mechanical Polish (CMP) technologies. As a result, trench opening can be enlarged without reducing the gate length of the transfer transistor.
AB - We present a new trench type cell, transistor on capacitor (TOC) cell with 1/4 pitch layout. Two kinds of new idea have been implemented. One is that the density of the trench capacitor is closest packed by introducing 1/4 pitch layout. The other is that the transfer transistor is fabricated over the trench capacitor by introducing the newly developed epitaxial growth and Chemical Mechanical Polish (CMP) technologies. As a result, trench opening can be enlarged without reducing the gate length of the transfer transistor.
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M3 - Conference article
AN - SCOPUS:0033700303
SN - 0743-1562
SP - 82
EP - 83
JO - Digest of Technical Papers - Symposium on VLSI Technology
JF - Digest of Technical Papers - Symposium on VLSI Technology
T2 - 2000 Symposium on VLSI Technology
Y2 - 13 June 2000 through 15 June 2000
ER -