Tungsten through-silicon via (W-TSV) technology is investigated for the fabrication of three-dimensional (3D) LSI chips having low-resistive TSVs with a width less than 3 μm. In our 3D integration technology, completed two-dimensional (2D) LSI chips including metal-oxide-semiconductor field-effect transistors (MOSFETs) and metal wirings are vertically stacked through a number of short vertical interconnections called TSV with lengths ranging from several microns to several tens of microns. The W-TSV technology is mainly divided into three low-temperature processes: deep-trench etching, dielectric layer formation, and filling with a conductive material. We successfully formed deep Si trenches through a 6-μm-thick SiO2 dielectric layer by the modified Bosch process. The depth of the resulting Si trenches with a dielectric layer is approximately 40 μm. A SiO2 layer was formed at the bottom and on the sidewall of the Si trenches by sub-atmospheric chemical vapor deposition (SACVD) method using tetraethylorthosilicate (TEOS) and O 3. In addition, we succeeded in uniformly depositing a conformal W metal layer by time-modulated W-CVD method at 300°C.
- Deep-trench etching
- Sub-atmospheric chemical vapor deposition
- Three-dimensional integration technology
- Through-silicon via (TSV)
- Time-modulated CVD method