In this paper Static Induction Transistor CMOS is analyzed by a circuit simulation method. According to the results, the propagation delay time of the SIT CMOS could be represented as the ratio of the load capacitance over the transconductance. The U-grooved structure plays an important role in the fabrication of MOS SIT with large transconductance and small parasitic capacitance. U-grooved SIT CMOS has been fabricated by anisotropic plasma etching, and its switching speed has been evaluated by a 31-stage ring oscillator. A minimum p-τ product of 3 fJ/gate has been obtained for a design rule of 1-µm channel length. A minimum propagation delay time of 49 ps/gate has also been obtained at a dissipation power of 7 mW/gate, which corresponds to a p-τ product of 350 fJ/gate.