Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC-SNUFEC VLSI

Katsuhiko Kawazoe, Shunji Honda, Shuji Kubota, Shuuzou Kato

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)


An Ultra-high-speed (higher than 60Mbps) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-μm semi-custom CMOS LSIC technology. To reduce the power consumption of the one-chip high-coding-rate Viterbi decoder, a newly developed universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been employed. In addition, a new maximum-likelihood-decision (MLD) circuit of the SST Viterbi decoder has been developed to reduce the path memory length without coding-gain degradation. The developed Viterbi decoder VLSIC achieves a maximum data rate of 60Mbps with a power consumption of 2.5W and achieves near theoretical net coding-gain performance for various coding rates.

Original languageEnglish
Title of host publicationIEEE International Conference on Communications
PublisherPubl by IEEE
Number of pages5
ISBN (Print)0780309510
Publication statusPublished - 1993 Jan 1
EventProceedings of the IEEE International Conference on Communications '93 - Geneva, Switz
Duration: 1993 May 231993 May 26

Publication series

NameIEEE International Conference on Communications


OtherProceedings of the IEEE International Conference on Communications '93
CityGeneva, Switz

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering


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