TY - GEN
T1 - Ultra-low power brain-inspired processors and neuromorphic processors with CMOS/MTJ hybrid technology
AU - Endoh, Tetsuo
N1 - Funding Information:
This work was supported by STT-MRAM R&D PROGRAM of CIES Consortium, and JST-OPERA.
Publisher Copyright:
© 2019 JSAP.
PY - 2019/6
Y1 - 2019/6
N2 - In this invited Plenary-talk, technologies regarding to STT-MRAM and NVLogic such as NV-AI VLSIs with CMOS/MTJ Hybrid technology are reviewed with our recent research results including fabricated chips.
AB - In this invited Plenary-talk, technologies regarding to STT-MRAM and NVLogic such as NV-AI VLSIs with CMOS/MTJ Hybrid technology are reviewed with our recent research results including fabricated chips.
UR - http://www.scopus.com/inward/record.url?scp=85070932696&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85070932696&partnerID=8YFLogxK
U2 - 10.23919/SNW.2019.8782898
DO - 10.23919/SNW.2019.8782898
M3 - Conference contribution
AN - SCOPUS:85070932696
T3 - 2019 Silicon Nanoelectronics Workshop, SNW 2019
BT - 2019 Silicon Nanoelectronics Workshop, SNW 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th Silicon Nanoelectronics Workshop, SNW 2019
Y2 - 9 June 2019 through 10 June 2019
ER -