TY - GEN
T1 - Ultra-low series resistance W/ErSi2/n+-Si and W/Pd2Si/p+-Si S/D electrodes for advanced CMOS platform
AU - Kuroda, Rihito
AU - Tanaka, Hiroaki
AU - Nakao, Yukihisa
AU - Teramoto, Akinobu
AU - Miyamoto, Naoto
AU - Sugawa, Shigetoshi
AU - Ohmi, Tadahiro
PY - 2010
Y1 - 2010
N2 - A formation technology of ultra-low series resistance CMOS source/drain (S/D) electrodes is developed. The silicide/silicon contact resistivity (R c) of 8.0×10-10 Ω·cm2 and the electrode's sheet resistance (Rsheet) of less than 5.0 Ω/□ are achieved for both n- and pMOS using W/ErSi2 and W/Pd2Si metal stacked silicide structures. For the first time, FD-SOI CMOS with the developed S/D electrodes was fabricated and the ring oscillator speed performance was evaluated.
AB - A formation technology of ultra-low series resistance CMOS source/drain (S/D) electrodes is developed. The silicide/silicon contact resistivity (R c) of 8.0×10-10 Ω·cm2 and the electrode's sheet resistance (Rsheet) of less than 5.0 Ω/□ are achieved for both n- and pMOS using W/ErSi2 and W/Pd2Si metal stacked silicide structures. For the first time, FD-SOI CMOS with the developed S/D electrodes was fabricated and the ring oscillator speed performance was evaluated.
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U2 - 10.1109/IEDM.2010.5703425
DO - 10.1109/IEDM.2010.5703425
M3 - Conference contribution
AN - SCOPUS:79951836890
SN - 9781424474196
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 26.2.1-26.2.4
BT - 2010 IEEE International Electron Devices Meeting, IEDM 2010
T2 - 2010 IEEE International Electron Devices Meeting, IEDM 2010
Y2 - 6 December 2010 through 8 December 2010
ER -