Ultra thin soi-pmosfet with elevated S/D and buried back gate

H. Oh; T. Sakaguchi; J. Shim; T. Fukushima; H. Kurino; M. Koyanagi

Ultra thin soi-pmosfet with elevated S/D and buried back gate

H. Oh, T. Sakaguchi, J. Shim, T. Fukushima, H. Kurino, M. Koyanagi

ENG - Mechanical Systems Engineering

Tohoku University

Research output: Contribution to conference › Paper › peer-review

Abstract

We have proposed ultra thin FD-SOIMOSFETs with buried back gate to control their threshold voltage. They have elevated S/D with Ni suicide to improve current drivability. In this work, we fabricated ultra thin FD-SOI PMOSFETs with buried back gate and successfully control their threshold voltage. We also studied the effect of ion implantation on surface morphology of Si selectively epitaxial growth to form elevated S/D.

Original language	English
Pages	51-56
Number of pages	6
Publication status	Published - 2004
Event	3rd International Conference on Semiconductor Technology, ISTC2004 - Shanghai, China Duration: 2004 Sept 15 → 2004 Sept 17

Conference

Conference	3rd International Conference on Semiconductor Technology, ISTC2004
Country/Territory	China
City	Shanghai
Period	04/9/15 → 04/9/17

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Cite this

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title = "Ultra thin soi-pmosfet with elevated S/D and buried back gate",

abstract = "We have proposed ultra thin FD-SOIMOSFETs with buried back gate to control their threshold voltage. They have elevated S/D with Ni suicide to improve current drivability. In this work, we fabricated ultra thin FD-SOI PMOSFETs with buried back gate and successfully control their threshold voltage. We also studied the effect of ion implantation on surface morphology of Si selectively epitaxial growth to form elevated S/D.",

author = "H. Oh and T. Sakaguchi and J. Shim and T. Fukushima and H. Kurino and M. Koyanagi",

year = "2004",

language = "English",

pages = "51--56",

note = "3rd International Conference on Semiconductor Technology, ISTC2004 ; Conference date: 15-09-2004 Through 17-09-2004",

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TY - CONF

T1 - Ultra thin soi-pmosfet with elevated S/D and buried back gate

AU - Oh, H.

AU - Sakaguchi, T.

AU - Shim, J.

AU - Fukushima, T.

AU - Kurino, H.

AU - Koyanagi, M.

PY - 2004

Y1 - 2004

N2 - We have proposed ultra thin FD-SOIMOSFETs with buried back gate to control their threshold voltage. They have elevated S/D with Ni suicide to improve current drivability. In this work, we fabricated ultra thin FD-SOI PMOSFETs with buried back gate and successfully control their threshold voltage. We also studied the effect of ion implantation on surface morphology of Si selectively epitaxial growth to form elevated S/D.

AB - We have proposed ultra thin FD-SOIMOSFETs with buried back gate to control their threshold voltage. They have elevated S/D with Ni suicide to improve current drivability. In this work, we fabricated ultra thin FD-SOI PMOSFETs with buried back gate and successfully control their threshold voltage. We also studied the effect of ion implantation on surface morphology of Si selectively epitaxial growth to form elevated S/D.

UR - http://www.scopus.com/inward/record.url?scp=28844496335&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=28844496335&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:28844496335

SP - 51

EP - 56

T2 - 3rd International Conference on Semiconductor Technology, ISTC2004

Y2 - 15 September 2004 through 17 September 2004

ER -

Ultra thin soi-pmosfet with elevated S/D and buried back gate

Abstract

Conference

UN SDGs

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