TY - JOUR
T1 - Ultrafast low-power operation of p+-n+ double-gate SOI MOSFETs
AU - Tanaka, Tetsu
AU - Suzuki, Kunihiro
AU - Horie, Hiroshi
AU - Sugii, Toshihiro
PY - 1994
Y1 - 1994
N2 - In this study, p+-n+ double-gate SOI MOSFET's have been fabricated using direct bonded SOI wafers just 40 nm thick. These devices, with an appropriate Vth, have good short-channel behavior and a large drive current. Obtained is an inverter delay time of 43 ps at 1 V, and 27 ps at 2 V, for Lg = 0.19 μm. These are the fastest reported values for this gate length.
AB - In this study, p+-n+ double-gate SOI MOSFET's have been fabricated using direct bonded SOI wafers just 40 nm thick. These devices, with an appropriate Vth, have good short-channel behavior and a large drive current. Obtained is an inverter delay time of 43 ps at 1 V, and 27 ps at 2 V, for Lg = 0.19 μm. These are the fastest reported values for this gate length.
UR - http://www.scopus.com/inward/record.url?scp=0028583847&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0028583847&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0028583847
SN - 0743-1562
SP - 11
EP - 12
JO - Digest of Technical Papers - Symposium on VLSI Technology
JF - Digest of Technical Papers - Symposium on VLSI Technology
T2 - Proceedings of the 1994 Symposium on VLSI Technology
Y2 - 7 June 1994 through 9 June 1994
ER -