Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application

Y. X. Liu; T. Mastukawa; K. Endo; S. O'uchi; J. Tsukada; H. Yamauchi; Y. Ishikawa; K. Sakamoto; M. Masahara; T. Kamei; T. Hayashida; A. Ogura

doi:10.1109/ESSDERC.2011.6044199

Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application

Y. X. Liu, T. Mastukawa, K. Endo, S. O'uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, K. Sakamoto, M. Masahara, T. Kamei, T. Hayashida, A. Ogura

IFS - Global Collaborative Research and Education Center for Integrated Flow Science (IFS-GCORE)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

The threshold voltage (V_t) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior I_d-V_g characteristics are observed in the scaled poly-Si channel FinFETs with gate length (L_g) down to 54 nm or less. The standard deviation of V_t (σV_t) of poly-Si channel FinFETs was 3 times higher than that of crystal channel ones at the same gate oxide thickness (T_ox). However, the σV_t of poly-Si channel tri-gate flash memories after one program/erase (P/E) cycle became comparable to that of crystal channel ones. Moreover, it was found that punch-through voltage of the poly-Si channel tri-gate flash memory is as high as 4.6 V even L_g was down to 76 nm.

Original language	English
Title of host publication	ESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference
Pages	203-206
Number of pages	4
DOIs	https://doi.org/10.1109/ESSDERC.2011.6044199
Publication status	Published - 2011
Event	41st European Solid-State Device Research Conference, ESSDERC 2011 - Helsinki, Finland Duration: 2011 Sept 12 → 2011 Sept 16

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Conference

Conference	41st European Solid-State Device Research Conference, ESSDERC 2011
Country/Territory	Finland
City	Helsinki
Period	11/9/12 → 11/9/16

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Liu, Y. X., Mastukawa, T., Endo, K., O'uchi, S., Tsukada, J., Yamauchi, H., Ishikawa, Y., Sakamoto, K., Masahara, M., Kamei, T., Hayashida, T., & Ogura, A. (2011). Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application. In ESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference (pp. 203-206). Article 6044199 (European Solid-State Device Research Conference). https://doi.org/10.1109/ESSDERC.2011.6044199

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title = "Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application",

abstract = "The threshold voltage (Vt) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior Id-Vg characteristics are observed in the scaled poly-Si channel FinFETs with gate length (Lg) down to 54 nm or less. The standard deviation of Vt (σVt) of poly-Si channel FinFETs was 3 times higher than that of crystal channel ones at the same gate oxide thickness (Tox). However, the σVt of poly-Si channel tri-gate flash memories after one program/erase (P/E) cycle became comparable to that of crystal channel ones. Moreover, it was found that punch-through voltage of the poly-Si channel tri-gate flash memory is as high as 4.6 V even Lg was down to 76 nm.",

author = "Liu, {Y. X.} and T. Mastukawa and K. Endo and S. O'uchi and J. Tsukada and H. Yamauchi and Y. Ishikawa and K. Sakamoto and M. Masahara and T. Kamei and T. Hayashida and A. Ogura",

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doi = "10.1109/ESSDERC.2011.6044199",

language = "English",

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series = "European Solid-State Device Research Conference",

pages = "203--206",

booktitle = "ESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference",

note = "41st European Solid-State Device Research Conference, ESSDERC 2011 ; Conference date: 12-09-2011 Through 16-09-2011",

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Liu, YX, Mastukawa, T, Endo, K, O'uchi, S, Tsukada, J, Yamauchi, H, Ishikawa, Y, Sakamoto, K, Masahara, M, Kamei, T, Hayashida, T & Ogura, A 2011, Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application. in ESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference., 6044199, European Solid-State Device Research Conference, pp. 203-206, 41st European Solid-State Device Research Conference, ESSDERC 2011, Helsinki, Finland, 11/9/12. https://doi.org/10.1109/ESSDERC.2011.6044199

Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application. / Liu, Y. X.; Mastukawa, T.; Endo, K. et al.
ESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference. 2011. p. 203-206 6044199 (European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Liu, Y. X.

AU - Mastukawa, T.

AU - Endo, K.

AU - O'uchi, S.

AU - Tsukada, J.

AU - Yamauchi, H.

AU - Ishikawa, Y.

AU - Sakamoto, K.

AU - Masahara, M.

AU - Kamei, T.

AU - Hayashida, T.

AU - Ogura, A.

PY - 2011

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N2 - The threshold voltage (Vt) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior Id-Vg characteristics are observed in the scaled poly-Si channel FinFETs with gate length (Lg) down to 54 nm or less. The standard deviation of Vt (σVt) of poly-Si channel FinFETs was 3 times higher than that of crystal channel ones at the same gate oxide thickness (Tox). However, the σVt of poly-Si channel tri-gate flash memories after one program/erase (P/E) cycle became comparable to that of crystal channel ones. Moreover, it was found that punch-through voltage of the poly-Si channel tri-gate flash memory is as high as 4.6 V even Lg was down to 76 nm.

AB - The threshold voltage (Vt) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior Id-Vg characteristics are observed in the scaled poly-Si channel FinFETs with gate length (Lg) down to 54 nm or less. The standard deviation of Vt (σVt) of poly-Si channel FinFETs was 3 times higher than that of crystal channel ones at the same gate oxide thickness (Tox). However, the σVt of poly-Si channel tri-gate flash memories after one program/erase (P/E) cycle became comparable to that of crystal channel ones. Moreover, it was found that punch-through voltage of the poly-Si channel tri-gate flash memory is as high as 4.6 V even Lg was down to 76 nm.

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BT - ESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference

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Y2 - 12 September 2011 through 16 September 2011

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Liu YX, Mastukawa T, Endo K, O'uchi S, Tsukada J, Yamauchi H et al. Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application. In ESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference. 2011. p. 203-206. 6044199. (European Solid-State Device Research Conference). doi: 10.1109/ESSDERC.2011.6044199

Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application

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