TY - GEN
T1 - VLSI design of a neural network model for detecting planar surface from local image motion
AU - Akima, Hisanao
AU - Moriya, Satoshi
AU - Kawakami, Susumu
AU - Yano, Masafumi
AU - Nakajima, Koji
AU - Sakurabah, Masao
AU - Sato, Shigeo
N1 - Publisher Copyright:
© Springer International Publishing Switzerland 2016.
PY - 2016
Y1 - 2016
N2 - The spatial perception, in which objects motion and position are recognized in 3-D like humans, has been demanding for applications such as an autonomous mobile robot and an autonomous car. Biologically inspired methods with dedicated hardware have been attractive because of its high energy efficiency compared with image processing algorithms performed on a CPU. We have focused on planar surface detection by using a neural network model proposed by Kawakami et al. [1, 2] and implemented this model on a VLSI. In the Kawakami model, the orientation and time-to-contact (TTC) of a planar surface are detected in two steps. First, local image motions are detected in motion detection cells (MDCs) from local retinal images. Second, the local image motions are integrated by accumulating MDC responses in medial superior temporal (MST) cells. In this study, we focused on the second step. The MDC responses are given as inputs to a VLSI. The neural connections between MDCs and MST cells are determined by using polar and cross-ratio transforms [2]. One of the main issues in implementing this step on a VLSI is wiring of these huge connections. We solved this by using virtual connection scheme with connection tables and packet-based communication. We designed a VLSI chip by using TSMC 65nm CMOS standard cell library in 1.32 mm×1.32 mm core area. The chip includes 64 processing elements (PEs) and each PE corresponds to an MST cell. Each PE has a connection table stored in a local memory, and a register to accumulate MDC responses. The orientation and TTC of a planar surface are detected from a location of the PE which has the maximum value. The latency required to accumulate all MDC responses and retrieve all PEs’ register values was estimated as 2.2 ms in a 100MHz operation by using gate-level HDL simulation. The power consumption was also estimated as 36mW. The operation speed of the designed VLSI is comparable with a C++ program performed on a CPU (Intel Core i7-3770, 3.4GHz, TDP 77 W), while its power consumption is smaller than the CPU by less than 1%.
AB - The spatial perception, in which objects motion and position are recognized in 3-D like humans, has been demanding for applications such as an autonomous mobile robot and an autonomous car. Biologically inspired methods with dedicated hardware have been attractive because of its high energy efficiency compared with image processing algorithms performed on a CPU. We have focused on planar surface detection by using a neural network model proposed by Kawakami et al. [1, 2] and implemented this model on a VLSI. In the Kawakami model, the orientation and time-to-contact (TTC) of a planar surface are detected in two steps. First, local image motions are detected in motion detection cells (MDCs) from local retinal images. Second, the local image motions are integrated by accumulating MDC responses in medial superior temporal (MST) cells. In this study, we focused on the second step. The MDC responses are given as inputs to a VLSI. The neural connections between MDCs and MST cells are determined by using polar and cross-ratio transforms [2]. One of the main issues in implementing this step on a VLSI is wiring of these huge connections. We solved this by using virtual connection scheme with connection tables and packet-based communication. We designed a VLSI chip by using TSMC 65nm CMOS standard cell library in 1.32 mm×1.32 mm core area. The chip includes 64 processing elements (PEs) and each PE corresponds to an MST cell. Each PE has a connection table stored in a local memory, and a register to accumulate MDC responses. The orientation and TTC of a planar surface are detected from a location of the PE which has the maximum value. The latency required to accumulate all MDC responses and retrieve all PEs’ register values was estimated as 2.2 ms in a 100MHz operation by using gate-level HDL simulation. The power consumption was also estimated as 36mW. The operation speed of the designed VLSI is comparable with a C++ program performed on a CPU (Intel Core i7-3770, 3.4GHz, TDP 77 W), while its power consumption is smaller than the CPU by less than 1%.
KW - Neural network
KW - VLSI
KW - Vision processing
UR - http://www.scopus.com/inward/record.url?scp=84988040465&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84988040465&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84988040465
SN - 9783319447773
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 556
EP - 557
BT - Artificial Neural Networks and Machine Learning - 25th International Conference on Artificial Neural Networks, ICANN 2016, Proceedings
A2 - Villa, Alessandro E.P.
A2 - Masulli, Paolo
A2 - Rivero, Antonio Javier Pons
PB - Springer Verlag
T2 - 25th International Conference on Artificial Neural Networks, ICANN 2016
Y2 - 6 September 2016 through 9 September 2016
ER -
