What can we do about barrier layer scaling to 5 nm node technology ?

Junichi Koike

doi:10.1109/VLSIT.2014.6894408

What can we do about barrier layer scaling to 5 nm node technology ?

Junichi Koike

ENG - Materials Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Interconnect-related problems in the advanced technology node are identified and possible solutions are proposed. A PVD process of a double-layer Ta/TaN barrier is to be replaced with a CVD process of a single-layer barrier. Cu filling process can be changed from PVD seed deposition and electroplating to dynamic PVD reflow of Cu. Manganese and its oxide are shown as a possible choice of new barrier materials.

Original language	English
Title of host publication	Digest of Technical Papers - Symposium on VLSI Technology
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479933310
DOIs	https://doi.org/10.1109/VLSIT.2014.6894408
Publication status	Published - 2014 Sept 8
Event	34th Symposium on VLSI Technology, VLSIT 2014 - Honolulu, United States Duration: 2014 Jun 9 → 2014 Jun 12

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Conference

Conference	34th Symposium on VLSI Technology, VLSIT 2014
Country/Territory	United States
City	Honolulu
Period	14/6/9 → 14/6/12

Access to Document

10.1109/VLSIT.2014.6894408

Cite this

@inproceedings{312d329ca417474082c01c684f872aa4,

title = "What can we do about barrier layer scaling to 5 nm node technology ?",

abstract = "Interconnect-related problems in the advanced technology node are identified and possible solutions are proposed. A PVD process of a double-layer Ta/TaN barrier is to be replaced with a CVD process of a single-layer barrier. Cu filling process can be changed from PVD seed deposition and electroplating to dynamic PVD reflow of Cu. Manganese and its oxide are shown as a possible choice of new barrier materials.",

author = "Junichi Koike",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 34th Symposium on VLSI Technology, VLSIT 2014 ; Conference date: 09-06-2014 Through 12-06-2014",

year = "2014",

month = sep,

day = "8",

doi = "10.1109/VLSIT.2014.6894408",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Digest of Technical Papers - Symposium on VLSI Technology",

address = "United States",

}

Koike, J 2014, What can we do about barrier layer scaling to 5 nm node technology ? in Digest of Technical Papers - Symposium on VLSI Technology., 6894408, Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., 34th Symposium on VLSI Technology, VLSIT 2014, Honolulu, United States, 14/6/9. https://doi.org/10.1109/VLSIT.2014.6894408

What can we do about barrier layer scaling to 5 nm node technology ? / Koike, Junichi.
Digest of Technical Papers - Symposium on VLSI Technology. Institute of Electrical and Electronics Engineers Inc., 2014. 6894408 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review