Naofumi Homma

Scopus著者プロファイル

h-index

年別の研究成果

112 会議への寄与
88 学術論文
9 編集
7 会議記事
その他

7 件

フィルター

2020
Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-
Regazzoni, F., Bhasin, S., Pour, A. A., Alshaer, I., Aydin, F., Aysu, A., Beroulle, V., Di Natale, G., Franzon, P., Hely, D., Homma, N., Ito, A., Jap, D., Kashyap, P., Polian, I., Potluri, S., Ueno, R., Vatajelu, E. I. & Yli-Mayry, V., 2020 11月 2, In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. 2020-November, 9256522.
研究成果: ジャーナルへの寄稿 › 会議記事 › 査読
18 被引用数 (Scopus)
2007
A high-performance ASIC implementation of the 64-bit block cipher CAST-128
Sugawara, T., Homma, N., Aoki, T. & Satoh, A., 2007, In: Proceedings - IEEE International Symposium on Circuits and Systems. p. 1859-1862 4 p., 4253024.
研究成果: ジャーナルへの寄稿 › 会議記事 › 査読

Open Access
3 被引用数 (Scopus)
DPA using phase-based waveform matching against random-delay countermeasure
Nagashima, S., Homma, N., Imai, Y., Aoki, T. & Satoh, A., 2007, In: Proceedings - IEEE International Symposium on Circuits and Systems. p. 1807-1810 4 p., 4253011.
研究成果: ジャーナルへの寄稿 › 会議記事 › 査読

Open Access
27 被引用数 (Scopus)
SPA against an FPGA-B ased RSA implementation with a high-radix montgomery multiplier
Miyamoto, A., Homma, N., Aoki, T. & Satoh, A., 2007, In: Proceedings - IEEE International Symposium on Circuits and Systems. p. 1847-1850 4 p., 4253021.
研究成果: ジャーナルへの寄稿 › 会議記事 › 査読
1 被引用数 (Scopus)
2004
A systematic approach for analyzing fast addition algorithms using counter tree diagrams
Homma, N., Sakiyama, J., Wakamatsu, T., Aoki, T. & Higuchi, T., 2004, In: Proceedings - IEEE International Symposium on Circuits and Systems. 5, p. V-197-V-200
研究成果: ジャーナルへの寄稿 › 会議記事 › 査読
7 被引用数 (Scopus)
Design and verification of parallel multipliers using arithmetic description language: ARITH
Ishida, K., Homma, N., Aoki, T. & Higuchi, T., 2004, In: Proceedings of The International Symposium on Multiple-Valued Logic. p. 334-339 6 p.
研究成果: ジャーナルへの寄稿 › 会議記事 › 査読
6 被引用数 (Scopus)
2003
A framework of evolutionary graph generation system and its application to circuit synthesis
Homma, N., Aoki, T., Motegi, M. & Higuchi, T., 2003, In: Proceedings - IEEE International Symposium on Circuits and Systems. 5, p. V201-V204
研究成果: ジャーナルへの寄稿 › 会議記事 › 査読
1 被引用数 (Scopus)

本間 尚文

研究成果

検索結果

Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-

A high-performance ASIC implementation of the 64-bit block cipher CAST-128

DPA using phase-based waveform matching against random-delay countermeasure

SPA against an FPGA-B ased RSA implementation with a high-radix montgomery multiplier

A systematic approach for analyzing fast addition algorithms using counter tree diagrams

Design and verification of parallel multipliers using arithmetic description language: ARITH

A framework of evolutionary graph generation system and its application to circuit synthesis

本間尚文