A 200 MHz Pipelined Multiplier Using 1.5 V-Supply Multiple-Valued MOS Current-Mode Circuits with Dual-Rail Source-Coupled Logic

Takahiro Hanyu, Michitaka Kameyama

研究成果: ジャーナルへの寄稿学術論文査読

90 被引用数 (Scopus)

抄録

A new multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current, the switching speed of the circuit is improved at low supply voltage. As an application to arithmetic systems, a 200 MHz 54 × 54-b pipelined multiplier using the proposed circuits with a 1.5 V supply voltage is designed with a 0.8-µm standard CMOS technology. The performance of the proposed multiplier is evaluated to be about 1.4 times faster than that of a corresponding binary implementation under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the multiple-valued arithmetic circuit.

本文言語英語
ページ(範囲)1239-1245
ページ数7
ジャーナルIEEE Journal of Solid-State Circuits
30
11
DOI
出版ステータス出版済み - 1995 11月

フィンガープリント

「A 200 MHz Pipelined Multiplier Using 1.5 V-Supply Multiple-Valued MOS Current-Mode Circuits with Dual-Rail Source-Coupled Logic」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル