A design of a Capacitorless 1T-DRAM Cell Using Gate-induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory

Eiji Yoshida, Tetsu Tanaka

研究成果: ジャーナルへの寄稿会議記事査読

23 被引用数 (Scopus)

抄録

A capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for write operation was demonstrated for the first time. Compared with the conventional write operation with impact ionization current, write operation with GIDL current provides low-power and high-speed operation. The capacitorless 1T-DRAM is the most promising technology for high performance embedded DRAM LSI.

本文言語英語
ページ(範囲)913-916
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
出版ステータス出版済み - 2003
イベントIEEE International Electron Devices Meeting - Washington, DC, 米国
継続期間: 2003 12月 82003 12月 10

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