TY - GEN
T1 - Architecture of an FPGA accelerator for LDA-based inference
AU - Ono, Taisuke
AU - Waidyasooriya, Hasitha Muthumala
AU - Hariyama, Masanori
AU - Ishigaki, Tsukasa
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/8/29
Y1 - 2017/8/29
N2 - Latent Dirichlet allocation (LDA) based topic inference is a data classification method, that is used efficiently for extremely large data sets. However, the processing time is very large due to the serial computational behavior of the Markov Chain Monte Carlo method used for the topic inference. We propose a pipelined hardware architecture and memory allocation scheme to accelerate LDA using parallel processing. The proposed architecture is implemented on a reconfigurable hardware called FPGA (field programmable gate array), using OpenCL design environment. According to the experimental results, we achieved maximum speed-up of 2.38 times, while maintaining the same quality compared to the conventional CPU-based implementation.
AB - Latent Dirichlet allocation (LDA) based topic inference is a data classification method, that is used efficiently for extremely large data sets. However, the processing time is very large due to the serial computational behavior of the Markov Chain Monte Carlo method used for the topic inference. We propose a pipelined hardware architecture and memory allocation scheme to accelerate LDA using parallel processing. The proposed architecture is implemented on a reconfigurable hardware called FPGA (field programmable gate array), using OpenCL design environment. According to the experimental results, we achieved maximum speed-up of 2.38 times, while maintaining the same quality compared to the conventional CPU-based implementation.
KW - Data classification
KW - Gibbs sampling
KW - Latent Dirichlet allocation
KW - Machine learning
KW - OpenCL for FPGA
UR - http://www.scopus.com/inward/record.url?scp=85030845149&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85030845149&partnerID=8YFLogxK
U2 - 10.1109/SNPD.2017.8022746
DO - 10.1109/SNPD.2017.8022746
M3 - Conference contribution
AN - SCOPUS:85030845149
T3 - Proceedings - 18th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2017
SP - 357
EP - 362
BT - Proceedings - 18th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2017
A2 - Hirata, Hiroaki
A2 - Hiroki, Nomiya
A2 - Hochin, Teruhisa
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 18th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2017
Y2 - 26 June 2017 through 28 June 2017
ER -