Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing

Takahiro Hanyu; Masanori Natsui; Daisuke Suzuki; Akira Mochizuki; Naoya Onizawa; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno

doi:10.1109/S3S.2015.7333502

Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing

Takahiro Hanyu, Masanori Natsui, Daisuke Suzuki, Akira Mochizuki, Naoya Onizawa, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

Novel logic-LSI architecture, 'nonvolatile logic-in-memory (NV-LIM) architecture,' where nonvolatile storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.

本文言語	English
ホスト出版物のタイトル	2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
出版社	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子版）	9781509002597
DOI	https://doi.org/10.1109/S3S.2015.7333502
出版ステータス	Published - 2015 11月 20
イベント	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 - Rohnert Park, United States 継続期間: 2015 10月 5 → 2015 10月 8

出版物シリーズ

名前	2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

Other

Other	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
国/地域	United States
City	Rohnert Park
Period	15/10/5 → 15/10/8

ASJC Scopus subject areas

電子工学および電気工学

文献へのアクセス

10.1109/S3S.2015.7333502

他のファイルとリンク

引用スタイル

Hanyu, T., Natsui, M., Suzuki, D., Mochizuki, A., Onizawa, N., Ikeda, S., Endoh, T., & Ohno, H. (2015). Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 [7333502] (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2015.7333502

Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing. / Hanyu, Takahiro ; Natsui, Masanori; Suzuki, Daisuke その他.
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7333502 (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015).

研究成果: Conference contribution

Hanyu, T , Natsui, M, Suzuki, D, Mochizuki, A, Onizawa, N , Ikeda, S , Endoh, T & Ohno, H 2015, Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing. in 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015., 7333502, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015, Institute of Electrical and Electronics Engineers Inc., IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015, Rohnert Park, United States, 15/10/5. https://doi.org/10.1109/S3S.2015.7333502

Hanyu T , Natsui M, Suzuki D, Mochizuki A, Onizawa N , Ikeda S その他. Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7333502. (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015). doi: 10.1109/S3S.2015.7333502

Hanyu, Takahiro ; Natsui, Masanori ; Suzuki, Daisuke その他. / Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing. 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015).

@inproceedings{5ad9d6f18c944488aec50e032a5976f5,

title = "Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing",

abstract = "Novel logic-LSI architecture, 'nonvolatile logic-in-memory (NV-LIM) architecture,' where nonvolatile storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.",

author = "Takahiro Hanyu and Masanori Natsui and Daisuke Suzuki and Akira Mochizuki and Naoya Onizawa and Shoji Ikeda and Tetsuo Endoh and Hideo Ohno",

year = "2015",

month = nov,

day = "20",

doi = "10.1109/S3S.2015.7333502",

language = "English",

series = "2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015",

note = "IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 ; Conference date: 05-10-2015 Through 08-10-2015",

}

TY - GEN

T1 - Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing

AU - Hanyu, Takahiro

AU - Natsui, Masanori

AU - Suzuki, Daisuke

AU - Mochizuki, Akira

AU - Onizawa, Naoya

AU - Ikeda, Shoji

AU - Endoh, Tetsuo

AU - Ohno, Hideo

PY - 2015/11/20

Y1 - 2015/11/20

N2 - Novel logic-LSI architecture, 'nonvolatile logic-in-memory (NV-LIM) architecture,' where nonvolatile storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.

AB - Novel logic-LSI architecture, 'nonvolatile logic-in-memory (NV-LIM) architecture,' where nonvolatile storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.

UR - http://www.scopus.com/inward/record.url?scp=84961829031&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84961829031&partnerID=8YFLogxK

U2 - 10.1109/S3S.2015.7333502

DO - 10.1109/S3S.2015.7333502

M3 - Conference contribution

AN - SCOPUS:84961829031

T3 - 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

BT - 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

Y2 - 5 October 2015 through 8 October 2015

ER -

Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing

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出版物シリーズ

Other

ASJC Scopus subject areas

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