A complementary pass gate (CP-gate) is proposed as a basic building block for a multiple-valued logic system. A CP-gate composed of two pass transistors and a down literal circuit realized with multiple-level ion implants has features of high density, low power dissipation, symmetry, and extensibility into an arbitrary multiple-valued logic system. An optimal network synthesis technique is also presented for a quaternary logic system with a minimized number of CP-gates.
|ホスト出版物のタイトル||Proceedings of The International Symposium on Multiple-Valued Logic|
|出版ステータス||Published - 1987 1月 1|
|名前||Proceedings of The International Symposium on Multiple-Valued Logic|
ASJC Scopus subject areas
- コンピュータ サイエンス（全般）
- 数学 (全般)