DESIGN OF A COMPLEMENTARY PASS GATE NETWORK FOR A MULTIPLE-VALUED LOGIC SYSTEM.

Kyu Ik Sohng; Michitaka Kameyama; Tatsuo Higuchi

DESIGN OF A COMPLEMENTARY PASS GATE NETWORK FOR A MULTIPLE-VALUED LOGIC SYSTEM.

Kyu Ik Sohng, Michitaka Kameyama, Tatsuo Higuchi

情報科学研究科・情報基礎科学専攻

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

A complementary pass gate (CP-gate) is proposed as a basic building block for a multiple-valued logic system. A CP-gate composed of two pass transistors and a down literal circuit realized with multiple-level ion implants has features of high density, low power dissipation, symmetry, and extensibility into an arbitrary multiple-valued logic system. An optimal network synthesis technique is also presented for a quaternary logic system with a minimized number of CP-gates.

本文言語	English
ホスト出版物のタイトル	Proceedings of The International Symposium on Multiple-Valued Logic
出版社	IEEE
ページ	142-149
ページ数	8
ISBN（印刷版）	0818607750
出版ステータス	Published - 1987 1月 1

出版物シリーズ

名前	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN（印刷版）	0195-623X

ASJC Scopus subject areas

コンピュータサイエンス（全般）
数学 (全般)

他のファイルとリンク

引用スタイル

@inproceedings{ef74532013b94ba4a3715a4a32970c1a,

title = "DESIGN OF A COMPLEMENTARY PASS GATE NETWORK FOR A MULTIPLE-VALUED LOGIC SYSTEM.",

abstract = "A complementary pass gate (CP-gate) is proposed as a basic building block for a multiple-valued logic system. A CP-gate composed of two pass transistors and a down literal circuit realized with multiple-level ion implants has features of high density, low power dissipation, symmetry, and extensibility into an arbitrary multiple-valued logic system. An optimal network synthesis technique is also presented for a quaternary logic system with a minimized number of CP-gates.",

author = "Sohng, {Kyu Ik} and Michitaka Kameyama and Tatsuo Higuchi",

year = "1987",

month = jan,

day = "1",

language = "English",

isbn = "0818607750",

series = "Proceedings of The International Symposium on Multiple-Valued Logic",

publisher = "IEEE",

pages = "142--149",

booktitle = "Proceedings of The International Symposium on Multiple-Valued Logic",

}

TY - GEN

T1 - DESIGN OF A COMPLEMENTARY PASS GATE NETWORK FOR A MULTIPLE-VALUED LOGIC SYSTEM.

AU - Sohng, Kyu Ik

AU - Kameyama, Michitaka

AU - Higuchi, Tatsuo

PY - 1987/1/1

Y1 - 1987/1/1

N2 - A complementary pass gate (CP-gate) is proposed as a basic building block for a multiple-valued logic system. A CP-gate composed of two pass transistors and a down literal circuit realized with multiple-level ion implants has features of high density, low power dissipation, symmetry, and extensibility into an arbitrary multiple-valued logic system. An optimal network synthesis technique is also presented for a quaternary logic system with a minimized number of CP-gates.

AB - A complementary pass gate (CP-gate) is proposed as a basic building block for a multiple-valued logic system. A CP-gate composed of two pass transistors and a down literal circuit realized with multiple-level ion implants has features of high density, low power dissipation, symmetry, and extensibility into an arbitrary multiple-valued logic system. An optimal network synthesis technique is also presented for a quaternary logic system with a minimized number of CP-gates.

UR - http://www.scopus.com/inward/record.url?scp=0023167197&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023167197&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0023167197

SN - 0818607750

T3 - Proceedings of The International Symposium on Multiple-Valued Logic

SP - 142

EP - 149

BT - Proceedings of The International Symposium on Multiple-Valued Logic

PB - IEEE

ER -

DESIGN OF A COMPLEMENTARY PASS GATE NETWORK FOR A MULTIPLE-VALUED LOGIC SYSTEM.

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出版物シリーズ

ASJC Scopus subject areas

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