TY - GEN
T1 - Design of a multi-context FPVLSI based on an asynchronous bit-serial architecture
AU - Muthumala, Waidyasooriya Hasitha
AU - Hariyama, Masanori
AU - Kameyama, Michitaka
PY - 2007/12/1
Y1 - 2007/12/1
N2 - This paper presents a novel asynchronous bitserial architecture for multi-context field programmable VLSIs (MC-FPVLSI). Conventional MC-FPVLSIs use global wires to distribute the context-ID signal. As a result, hardware utilization ratio decreases, since it is impossible to execute different contexts simultaneously. They also have a high power consumption and high area overhead due to the clock tree and context ID trees. The proposed MC-FPVLSI eliminates the clock tree and global context ID trees completely. It uses a locally distributed contextID signal and therefore, partial reconfiguration and simultaneous execution of different contexts are possible. It also uses the same wires to transfer the data and context ID signal, so that the area can be reduced further. The proposed architecture is designed using 6-metal 1-poly 90nm CMOS process technology.
AB - This paper presents a novel asynchronous bitserial architecture for multi-context field programmable VLSIs (MC-FPVLSI). Conventional MC-FPVLSIs use global wires to distribute the context-ID signal. As a result, hardware utilization ratio decreases, since it is impossible to execute different contexts simultaneously. They also have a high power consumption and high area overhead due to the clock tree and context ID trees. The proposed MC-FPVLSI eliminates the clock tree and global context ID trees completely. It uses a locally distributed contextID signal and therefore, partial reconfiguration and simultaneous execution of different contexts are possible. It also uses the same wires to transfer the data and context ID signal, so that the area can be reduced further. The proposed architecture is designed using 6-metal 1-poly 90nm CMOS process technology.
KW - Dynamically reconfigurable
KW - FPGA
KW - Self timing
UR - http://www.scopus.com/inward/record.url?scp=48349092739&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=48349092739&partnerID=8YFLogxK
U2 - 10.1109/DCAS.2007.4433216
DO - 10.1109/DCAS.2007.4433216
M3 - Conference contribution
AN - SCOPUS:48349092739
SN - 9781424416806
T3 - 2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07
SP - 59
EP - 62
BT - 2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC)
T2 - 2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07
Y2 - 15 November 2007 through 16 November 2007
ER -