TY - GEN
T1 - Exploring a design space of 3-D stacked vector processors
AU - Egawa, Ryusuke
AU - Tada, Jubee
AU - Kobayashi, Hiroaki
N1 - Copyright:
Copyright 2021 Elsevier B.V., All rights reserved.
PY - 2013
Y1 - 2013
N2 - Three dimensional (3-D) technologies have come under the spotlight to overcome limitations of conventional two dimensional (2-D) microprocessor implementations. However, the effect of 3-D integrations with vertical interconnects in future vector processors design is not well discussed yet. In this paper, aiming at exploring the design space of future vector processors, fine and coarse grain 3-D integrations that aggressively employ vertical interconnects are designed and evaluated.
AB - Three dimensional (3-D) technologies have come under the spotlight to overcome limitations of conventional two dimensional (2-D) microprocessor implementations. However, the effect of 3-D integrations with vertical interconnects in future vector processors design is not well discussed yet. In this paper, aiming at exploring the design space of future vector processors, fine and coarse grain 3-D integrations that aggressively employ vertical interconnects are designed and evaluated.
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U2 - 10.1007/978-3-642-32454-3_4
DO - 10.1007/978-3-642-32454-3_4
M3 - Conference contribution
AN - SCOPUS:84896597192
SN - 9783642324536
T3 - Sustained Simulation Performance 2012 - Proceedings of the Joint Workshop on High Performance Computing on Vector Systems, and Workshop on Sustained Simulation Performance
SP - 35
EP - 49
BT - Sustained Simulation Performance 2012 - Proceedings of the Joint Workshop on High Performance Computing on Vector Systems, and Workshop on Sustained Simulation Performance
PB - Springer Science and Business Media, LLC
T2 - Joint Workshop on High Performance Computing on Vector Systems and 15th Workshop on Sustained Simulation Performance 2012
Y2 - 1 March 2012 through 1 March 2012
ER -