Grain-orientation induced work function variation in nanoscale metal-gate transistors - Part II: Implications for process, device, and circuit design

This paper investigates the process, device, and circuit design implications of grain-orientation-induced work function variation (WFV) in high-$k$/metal-gate devices. WFV is caused by the dependence of the work function of metal grains on their orientations and is analytically modeled in the companion paper (part I). Using this modeling framework, various implications of WFV are investigated in this paper. It is shown that process designers can utilize the proposed models to reduce the impact of WFV by identifying proper materials and fabrication processes. For instance, four types of metal nitride gate materials (TiN and TaN for NMOS devices and WN and MoN for PMOS devices) are studied, and it is shown that TiN and WN result in lower V_th fluctuations. Moreover, device engineers can study the impact of WFV on various types of classical and nonclassical metal-gate CMOS transistors using these analytical models. As an example, it is shown that, for a given channel length, single-fin FinFETs are less affected by WFV compared to fully depleted SOI and bulk-Si devices due to their larger gate area. Furthermore, circuit designers can benefit from the proposed modeling framework that allows straightforward evaluation of the key performance and reliability parameters of the circuits under such V_th fluctuations. For instance, an SRAM cell is analyzed in the presence of V_th fluctuations due to WFV, and it is shown that such variations can result in considerable performance and reliability degradation.