High-density and high-speed 128Mb chain FeRAM™ with SDRAM-compatible DDR2 interface

Yoshiro Shimojo; Atsushi Konno; Jun Nishimura; Takayuki Okada; Yuki Yamada; Soichiro Kitazaki; Hironobu Furuhashi; Soichi Yamazaki; Katsunori Yahashi; Kazuhiro Tomioka; Yoshihiro Minami; Hiroyuki Kanaya; Susumu Shuto; Koji Yamakawa; Tohru Ozaki; Hidehiro Shiga; Tadashi Miyakawa; Shinichiro Shiratake; Daisaburo Takashima; Iwao Kunishima; Takeshi Hamamoto; Akihiro Nitayama

High-density and high-speed 128Mb chain FeRAM™ with SDRAM-compatible DDR2 interface

Yoshiro Shimojo, Atsushi Konno, Jun Nishimura, Takayuki Okada, Yuki Yamada, Soichiro Kitazaki, Hironobu Furuhashi, Soichi Yamazaki, Katsunori Yahashi, Kazuhiro Tomioka, Yoshihiro Minami, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Tohru Ozaki, Hidehiro Shiga, Tadashi Miyakawa, Shinichiro Shiratake, Daisaburo Takashima, Iwao KunishimaTakeshi Hamamoto, Akihiro Nitayama

国際集積エレクトロニクス研究開発センター

研究成果: Conference contribution

24 被引用数 (Scopus)

抄録

Novel cell technologies are successfully developed for the world's highest-density and highest-speed 128Mb chain FeRAMTM with SDRAM-compatible 1.6GByte/s DDR2 interface. To overcome the signal window reduction due to the capacitor shrinkage, new cell technologies such as half-pitch layout with triangular capacitors, advanced nestled chain structure, high-density cover film and low-damage etching technique are established. New architecture with small bit line capacitance of 60fF is also installed [1]. With these new technologies, the cell signal window reaches 380 mV, which is sufficient for stable 128Mb 1T1C operation.

本文言語	English
ホスト出版物のタイトル	2009 Symposium on VLSI Technology, VLSIT 2009
ページ	218-219
ページ数	2
出版ステータス	Published - 2009 11月 16
イベント	2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan 継続期間: 2009 6月 16 → 2009 6月 18

出版物シリーズ

名前	Digest of Technical Papers - Symposium on VLSI Technology
ISSN（印刷版）	0743-1562

Other

Other	2009 Symposium on VLSI Technology, VLSIT 2009
国/地域	Japan
City	Kyoto
Period	09/6/16 → 09/6/18

ASJC Scopus subject areas

電子工学および電気工学

他のファイルとリンク

引用スタイル

Shimojo, Y., Konno, A., Nishimura, J., Okada, T., Yamada, Y., Kitazaki, S., Furuhashi, H., Yamazaki, S., Yahashi, K., Tomioka, K., Minami, Y., Kanaya, H., Shuto, S., Yamakawa, K., Ozaki, T., Shiga, H., Miyakawa, T., Shiratake, S., Takashima, D., ... Nitayama, A. (2009). High-density and high-speed 128Mb chain FeRAM™ with SDRAM-compatible DDR2 interface. In 2009 Symposium on VLSI Technology, VLSIT 2009 (pp. 218-219). [5200605] (Digest of Technical Papers - Symposium on VLSI Technology).

Shimojo, Y, Konno, A, Nishimura, J, Okada, T, Yamada, Y, Kitazaki, S, Furuhashi, H, Yamazaki, S, Yahashi, K, Tomioka, K, Minami, Y, Kanaya, H, Shuto, S, Yamakawa, K, Ozaki, T, Shiga, H, Miyakawa, T, Shiratake, S, Takashima, D, Kunishima, I, Hamamoto, T & Nitayama, A 2009, High-density and high-speed 128Mb chain FeRAM™ with SDRAM-compatible DDR2 interface. in 2009 Symposium on VLSI Technology, VLSIT 2009., 5200605, Digest of Technical Papers - Symposium on VLSI Technology, pp. 218-219, 2009 Symposium on VLSI Technology, VLSIT 2009, Kyoto, Japan, 09/6/16.

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abstract = "Novel cell technologies are successfully developed for the world's highest-density and highest-speed 128Mb chain FeRAMTM with SDRAM-compatible 1.6GByte/s DDR2 interface. To overcome the signal window reduction due to the capacitor shrinkage, new cell technologies such as half-pitch layout with triangular capacitors, advanced nestled chain structure, high-density cover film and low-damage etching technique are established. New architecture with small bit line capacitance of 60fF is also installed [1]. With these new technologies, the cell signal window reaches 380 mV, which is sufficient for stable 128Mb 1T1C operation.",

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author = "Yoshiro Shimojo and Atsushi Konno and Jun Nishimura and Takayuki Okada and Yuki Yamada and Soichiro Kitazaki and Hironobu Furuhashi and Soichi Yamazaki and Katsunori Yahashi and Kazuhiro Tomioka and Yoshihiro Minami and Hiroyuki Kanaya and Susumu Shuto and Koji Yamakawa and Tohru Ozaki and Hidehiro Shiga and Tadashi Miyakawa and Shinichiro Shiratake and Daisaburo Takashima and Iwao Kunishima and Takeshi Hamamoto and Akihiro Nitayama",

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AU - Yamada, Yuki

AU - Kitazaki, Soichiro

AU - Furuhashi, Hironobu

AU - Yamazaki, Soichi

AU - Yahashi, Katsunori

AU - Tomioka, Kazuhiro

AU - Minami, Yoshihiro

AU - Kanaya, Hiroyuki

AU - Shuto, Susumu

AU - Yamakawa, Koji

AU - Ozaki, Tohru

AU - Shiga, Hidehiro

AU - Miyakawa, Tadashi

AU - Shiratake, Shinichiro

AU - Takashima, Daisaburo

AU - Kunishima, Iwao

AU - Hamamoto, Takeshi

AU - Nitayama, Akihiro

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AB - Novel cell technologies are successfully developed for the world's highest-density and highest-speed 128Mb chain FeRAMTM with SDRAM-compatible 1.6GByte/s DDR2 interface. To overcome the signal window reduction due to the capacitor shrinkage, new cell technologies such as half-pitch layout with triangular capacitors, advanced nestled chain structure, high-density cover film and low-damage etching technique are established. New architecture with small bit line capacitance of 60fF is also installed [1]. With these new technologies, the cell signal window reaches 380 mV, which is sufficient for stable 128Mb 1T1C operation.

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BT - 2009 Symposium on VLSI Technology, VLSIT 2009

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High-density and high-speed 128Mb chain FeRAM™ with SDRAM-compatible DDR2 interface

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