High-Speed Hardware Architecture for Post-Quantum Diffie-Hellman Key Exchange Based on Residue Number System

Rei Ueno, Naofumi Homma

研究成果: 書籍の章/レポート/Proceedings会議への寄与査読

抄録

This paper presents a hardware architecture for a post-quantum key exchange protocol, named super-singular isogeny Diffie-Hellman (SIDH). The proposed hardware employs residue number system (RNS) and is optimized to reduce the latency of \mathbb{F}-{p^{2}} multiplication and RNS Montgomery reduction, which are major time-consuming procedures in SIDH. The performance of the proposed hardware is validated and evaluated through an experimental implementation on Xilinx Kintex7 Ultrascale+. As a result, we confirm that the proposed hardware can perform an SIDH computation 34% faster than the state-of-the-art existing one on the same device at a resource overhead.

本文言語英語
ホスト出版物のタイトルIEEE International Symposium on Circuits and Systems, ISCAS 2022
出版社Institute of Electrical and Electronics Engineers Inc.
ページ2107-2111
ページ数5
ISBN(電子版)9781665484855
DOI
出版ステータス出版済み - 2022
イベント2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 - Austin, 米国
継続期間: 2022 5月 272022 6月 1

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
2022-May
ISSN(印刷版)0271-4310

会議

会議2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
国/地域米国
CityAustin
Period22/5/2722/6/1

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