The proposal of a hybrid gate dielectric systematically modulated with low-k material layer has been shown to be a promising strategy in the development of low-consumption field-effect transistors (FETs) with high performance. In this work, by fabricating KTaO3 FETs containing Y-doped Ta2O5/parylene-C hybrid gate dielectrics with different ratios of component thicknesses, we explored the dependence of the transistor electrical properties on the parylene-C layer thickness. Based on the results and analysis, an optimized transistor performance was achieved with an appropriate Y-doped Ta2O5/parylene-C thickness ratio from the point of view on low voltage operation. This study contributes to provide guidance for future device design and applications.
|ジャーナル||Journal of Applied Physics|
|出版ステータス||Published - 2016 1月 21|
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