TY - JOUR
T1 - Integrated voltage regulators with high-side NMOS power switch and dedicated bootstrap driver using vertical body channel MOSFET under 100MHz switching frequency for compact system and efficiency enhancement
AU - Itoh, Kazuki
AU - Muraguchi, Masakazu
AU - Endoh, Tetsuo
N1 - Publisher Copyright:
© 2017 The Japan Society of Applied Physics.
PY - 2017/4
Y1 - 2017/4
N2 - In this paper, integrated voltage regulators (IVRs) with a cascode bridge circuit composed of a high-side (HS) NMOS power switch and a dedicated bootstrap driver using a vertical body channel (BC) MOSFET are proposed for improving efficiency under 100MHz switching frequency. The proposed circuit utilizes the back-bias effect free characteristic of the vertical BC MOSFET without additional well structures such as a triple-well structure for efficiency enhancement. Power switching of twice the process voltage VMAX with an HS NMOS power switch is realized by a novel circuit technique that directly connects the bootstrap node to the gate of an n-type MOSFET connected to the input voltage. Moreover, by using a vertical BC MOSFET free from the back-bias effect, the on-resistance increase of the HS NMOS power switch due to the high input voltage is significantly suppressed, and the drain-to-source voltage of MOSFETs in the off-state is distributed uniformly in comparison with that of a planar MOSFET. The proposed IVR of 3.3V input voltage and 1.2V output voltage is designed and simulated by HSPICE. Additionally, the power transistor size dependence of efficiency indicated that the proposed IVR can achieve a 4.2% higher peak efficiency than the conventional IVR with a 26% smaller total power transistor size.
AB - In this paper, integrated voltage regulators (IVRs) with a cascode bridge circuit composed of a high-side (HS) NMOS power switch and a dedicated bootstrap driver using a vertical body channel (BC) MOSFET are proposed for improving efficiency under 100MHz switching frequency. The proposed circuit utilizes the back-bias effect free characteristic of the vertical BC MOSFET without additional well structures such as a triple-well structure for efficiency enhancement. Power switching of twice the process voltage VMAX with an HS NMOS power switch is realized by a novel circuit technique that directly connects the bootstrap node to the gate of an n-type MOSFET connected to the input voltage. Moreover, by using a vertical BC MOSFET free from the back-bias effect, the on-resistance increase of the HS NMOS power switch due to the high input voltage is significantly suppressed, and the drain-to-source voltage of MOSFETs in the off-state is distributed uniformly in comparison with that of a planar MOSFET. The proposed IVR of 3.3V input voltage and 1.2V output voltage is designed and simulated by HSPICE. Additionally, the power transistor size dependence of efficiency indicated that the proposed IVR can achieve a 4.2% higher peak efficiency than the conventional IVR with a 26% smaller total power transistor size.
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U2 - 10.7567/JJAP.56.04CF14
DO - 10.7567/JJAP.56.04CF14
M3 - Article
AN - SCOPUS:85017180346
SN - 0021-4922
VL - 56
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
IS - 4
M1 - 04CF14
ER -