TY - JOUR

T1 - Logic-in-control-architecture-based reconfigurable VLSI using multiple-valued differential-pair circuits

AU - Okada, Nobuaki

AU - Kameyama, Michitaka

N1 - Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.

PY - 2010/8

Y1 - 2010/8

N2 - A fine-grain bit-serial multiple-valued reconfigurable VLSI based on logic-in-control architecture is proposed for effective use of the hardware resources. In logic-in-control architecture, the control circuits can be merged with the arithmetic/logic circuits, where the control and arithmetic/logic circuits are constructed by using one or multiple logic blocks. To implement the control circuit, only one state in a state transition diagram is allocated to one logic block, which leads to reduction of the complexity of interconnections between logic blocks. The fine-grain logic block is implemented based on multiple-valued current-mode circuit technology. In the fine-grain logic block, an arbitrary 3-variable binary function can be programmed by using one multiplexer and two universal literal circuits. Three-variable binary functions are used to implement the control circuit. Moreover, the hardware resources can be utilized to construct a bit-serial adder, because full-adder sum and carry can be realized by programming in the universal literal circuit. Therefore, the logic block can be effectively reconfigured for arithmetic/logic and control circuits. It is made clear that the hardware complexity of the control circuit in the proposed reconfigurable VLSI can be reduced in comparison with that of the control circuit based on a typically sequential circuit in the conventional FPGA and the fine-grain field-programmable VLSI reported until now.

AB - A fine-grain bit-serial multiple-valued reconfigurable VLSI based on logic-in-control architecture is proposed for effective use of the hardware resources. In logic-in-control architecture, the control circuits can be merged with the arithmetic/logic circuits, where the control and arithmetic/logic circuits are constructed by using one or multiple logic blocks. To implement the control circuit, only one state in a state transition diagram is allocated to one logic block, which leads to reduction of the complexity of interconnections between logic blocks. The fine-grain logic block is implemented based on multiple-valued current-mode circuit technology. In the fine-grain logic block, an arbitrary 3-variable binary function can be programmed by using one multiplexer and two universal literal circuits. Three-variable binary functions are used to implement the control circuit. Moreover, the hardware resources can be utilized to construct a bit-serial adder, because full-adder sum and carry can be realized by programming in the universal literal circuit. Therefore, the logic block can be effectively reconfigured for arithmetic/logic and control circuits. It is made clear that the hardware complexity of the control circuit in the proposed reconfigurable VLSI can be reduced in comparison with that of the control circuit based on a typically sequential circuit in the conventional FPGA and the fine-grain field-programmable VLSI reported until now.

KW - Control circuit

KW - Direct allocation

KW - Fine-grain reconfigurable VLSI

KW - Multiple-valued current-mode logic

KW - Sequential logic circuit

UR - http://www.scopus.com/inward/record.url?scp=77956026555&partnerID=8YFLogxK

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U2 - 10.1587/transinf.E93.D.2126

DO - 10.1587/transinf.E93.D.2126

M3 - Article

AN - SCOPUS:77956026555

SN - 0916-8532

VL - E93-D

SP - 2126

EP - 2133

JO - IEICE Transactions on Information and Systems

JF - IEICE Transactions on Information and Systems

IS - 8

ER -