Multiple-valued logic-in-memory VLSI architecture based on floating-gate-MOS pass-transistor logic

Takahiro Hanyu, Michitaka Kameyama

研究成果: ジャーナルへの寄稿学術論文査読

16 被引用数 (Scopus)


A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logic-in-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The effective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-μm flash EEPROM technology.

ジャーナルIEICE Transactions on Electronics
出版ステータス出版済み - 1999


「Multiple-valued logic-in-memory VLSI architecture based on floating-gate-MOS pass-transistor logic」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。