— VLSI-oriented multiple-valued current-mode MOS arithmetic circuits using radix-2 signed-digit (SD) number representations are proposed. A prototype adder chip is implemented with 10-μm CMOS technology to confirm the principle operation. Furthermore, a new multiplication scheme using four-input current-mode wired summations is presented to realize a high-speed small-size multiplier. The designed 32 × 32-bit multiplier is composed of 18 800 transistors and required fewer interconnections. The multiply time is estimated to be 45 ns by SPICE simulation in 2-μm CMOS technology. It is shown that the developed technology is also potentially effective for the reduction of the data-bus area in VLSI.
|ジャーナル||IEEE Journal of Solid-State Circuits|
|出版ステータス||Published - 1990 2月|
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