TY - GEN
T1 - Novel oxygen showering process (OSP) for extreme damage suppression of sub-20nm high density p-MTJ array without IBE treatment
AU - Jeong, J. H.
AU - Endoh, T.
PY - 2015/8/25
Y1 - 2015/8/25
N2 - A novel damage recovery scheme using the oxygen showering post-treatment (OSP) is proposed to recover patterning damages and to improve electric and magnetic properties of p-MTJs, and its array yield. By applying our OSP to 25nm p-MTJs cell array, the MR was increased from 99% to 116% and the Isw was decreased from 41.1uA to 28.7uA. Moreover, electric short fails of MTJs array due to metallic by-products reduced dramatically by the selective oxidation of the damaged layer and its isolation from damage-less area. The OSP process makes the switching efficiency of 25nm patterned MTJs to be improved more than 30% compared with IBE treatment process. The mechanism of this enhancement is that spin directions of damaged area is changed from perpendicular to in-plane and, by this change, the energy barrier of damaged area is reduced. By the OSP treatment, we could develop the robust patterning process for sub-20nm STT-MRAM.
AB - A novel damage recovery scheme using the oxygen showering post-treatment (OSP) is proposed to recover patterning damages and to improve electric and magnetic properties of p-MTJs, and its array yield. By applying our OSP to 25nm p-MTJs cell array, the MR was increased from 99% to 116% and the Isw was decreased from 41.1uA to 28.7uA. Moreover, electric short fails of MTJs array due to metallic by-products reduced dramatically by the selective oxidation of the damaged layer and its isolation from damage-less area. The OSP process makes the switching efficiency of 25nm patterned MTJs to be improved more than 30% compared with IBE treatment process. The mechanism of this enhancement is that spin directions of damaged area is changed from perpendicular to in-plane and, by this change, the energy barrier of damaged area is reduced. By the OSP treatment, we could develop the robust patterning process for sub-20nm STT-MRAM.
KW - Damage recovery
KW - MRAM
KW - MTJs
KW - selective oxidation
KW - short yield
KW - switching efficiency
UR - http://www.scopus.com/inward/record.url?scp=84950997418&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84950997418&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2015.7223660
DO - 10.1109/VLSIT.2015.7223660
M3 - Conference contribution
AN - SCOPUS:84950997418
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - T158-T159
BT - 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Symposium on VLSI Technology, VLSI Technology 2015
Y2 - 16 June 2015 through 18 June 2015
ER -