NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors

Tohru Miwa; Junichi Yamada; Hiroki Koike; Hideo Toyoshima; Kazushi Amanuma; Sota Kobayashi; Toru Tatsumi; Yukihiro Maejima; Hiromitsu Hada; Takemitsu Kunio

NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors

Tohru Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiro Maejima, Hiromitsu Hada, Takemitsu Kunio

研究成果: Conference article › 査読

2 被引用数 (Scopus)

抄録

This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell are overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.

本文言語	English
ページ（範囲）	65-68
ページ数	4
ジャーナル	Proceedings of the Custom Integrated Circuits Conference
出版ステータス	Published - 2000 1月 1
外部発表	はい
イベント	CICC 2000: 22nd Annual Custom Integrated Circuits Conference - Orlando, FL, USA 継続期間: 2000 5月 21 → 2000 5月 24

ASJC Scopus subject areas

電子工学および電気工学

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引用スタイル

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title = "NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors",

abstract = "This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell are overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.",

author = "Tohru Miwa and Junichi Yamada and Hiroki Koike and Hideo Toyoshima and Kazushi Amanuma and Sota Kobayashi and Toru Tatsumi and Yukihiro Maejima and Hiromitsu Hada and Takemitsu Kunio",

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AU - Miwa, Tohru

AU - Yamada, Junichi

AU - Koike, Hiroki

AU - Toyoshima, Hideo

AU - Amanuma, Kazushi

AU - Kobayashi, Sota

AU - Tatsumi, Toru

AU - Maejima, Yukihiro

AU - Hada, Hiromitsu

AU - Kunio, Takemitsu

PY - 2000/1/1

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N2 - This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell are overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.

AB - This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell are overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.

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Y2 - 21 May 2000 through 24 May 2000

ER -

NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors

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ASJC Scopus subject areas

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