Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations

Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Matsukawa, K. Endo, S. O'uchi, Y. X. Liu, M. Masahara, H. Ota

研究成果: 書籍の章/レポート/Proceedings会議への寄与査読

5 被引用数 (Scopus)

抄録

The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field, was evaluated. The TFET was fabricated by inserting a parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer. We also propose a scheme to improve the performance of the TFETs by modification of the gate and channel configurations.

本文言語英語
ホスト出版物のタイトルESSDERC 2013 - Proceedings of the 43rd European Solid-State Device Research Conference
出版社IEEE Computer Society
ページ45-48
ページ数4
ISBN(印刷版)9781479906499
DOI
出版ステータス出版済み - 2013
イベント43rd European Solid-State Device Research Conference, ESSDERC 2013 - Bucharest, ルーマニア
継続期間: 2013 9月 162013 9月 20

出版物シリーズ

名前European Solid-State Device Research Conference
ISSN(印刷版)1930-8876

会議

会議43rd European Solid-State Device Research Conference, ESSDERC 2013
国/地域ルーマニア
CityBucharest
Period13/9/1613/9/20

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