TY - GEN
T1 - PMAC++:incrementalmac scheme adaptableto lightweight block ciphers
AU - Oda, Maya
AU - Veno, Rei
AU - Inoue, Akiko
AU - Minematsu, Kazuhiko
AU - Homma, Naofumi
N1 - Publisher Copyright:
© 2020 IEEE
PY - 2020
Y1 - 2020
N2 - This paper presents anew incremental parallelizablemessage authentication code(MAC)scheme adaptable to lightweight blockciphersfor memory integrity verification.The highlight ofthe proposed schemeistoachieveboth incremental update capability and sufficient security bound with lightweight block ciphers, whichisanovel feature. Weextendtheconventional parallelizable MACtorealizethe incremental update capability whilekeepingthe original security bound. Weprove that a comparable security bound canbe obtained evenifthis changeis incorporated. Wealso present a hardware architecture forthe proposed MACschemewith lightweight block ciphers and demonstrate theeffectiveness through FPGA implementation. The evaluation results indicate that the proposed MAC hardware achieves3.4times improvement inthe latency-area product for thetag update compared with the conventional MAC.
AB - This paper presents anew incremental parallelizablemessage authentication code(MAC)scheme adaptable to lightweight blockciphersfor memory integrity verification.The highlight ofthe proposed schemeistoachieveboth incremental update capability and sufficient security bound with lightweight block ciphers, whichisanovel feature. Weextendtheconventional parallelizable MACtorealizethe incremental update capability whilekeepingthe original security bound. Weprove that a comparable security bound canbe obtained evenifthis changeis incorporated. Wealso present a hardware architecture forthe proposed MACschemewith lightweight block ciphers and demonstrate theeffectiveness through FPGA implementation. The evaluation results indicate that the proposed MAC hardware achieves3.4times improvement inthe latency-area product for thetag update compared with the conventional MAC.
KW - Crypto graphic hard ware architecture
KW - Light weight blockciphers
KW - Memory security
KW - Message authentication code
UR - http://www.scopus.com/inward/record.url?scp=85109297294&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85109297294&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:85109297294
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
Y2 - 10 October 2020 through 21 October 2020
ER -