抄録
This paper presents a hardware algorithm for a real/complex reconfigurable arithmetic unit, which can change its structure for three different arithmetic, modes in real time. The three modes realize (i) a single-precision complex-number multiplication, (ii) a double-precision real-number multiplication, and (iii) a pair of single-precision real-number four-operand multiply-add operations, respectively. We discuss the reconfiguration of hardware structure on the basis of the transformation of the number system used in each arithmetic mode. The designed arithmetic unit can perform high-speed real/complex arithmetic computations based on binary-tree addition scheme, and also exhibits highly regular structure suited for VLSI implementation.
| 本文言語 | 英語 |
|---|---|
| ページ | 200-207 |
| ページ数 | 8 |
| 出版ステータス | 出版済み - 1997 |
| イベント | Proceedings of the 1997 13th IEEE Symposium on Computer Arithmetic - Asilomar, CA, USA 継続期間: 1997 7月 6 → 1997 7月 9 |
会議
| 会議 | Proceedings of the 1997 13th IEEE Symposium on Computer Arithmetic |
|---|---|
| City | Asilomar, CA, USA |
| Period | 97/7/6 → 97/7/9 |