This paper proposes a collision warning system that gives a warning to a driver by detecting a hazard during driving. This system has a configuration based on the fail-safe concept that gives a warning to the driver by determining the state of danger when a path that the vehicle cannot safely drive on cannot be found within a certain processing time. Furthermore, it proposes a road extraction VLSI processor for a highly safe vehicle based on the logic-in-memory architecture, which eliminates transfer bottlenecks by integrating the memory and the functional units. This VLSI processor uses a VLSI-oriented algorithm based on regular repetitions of local parallel processing of external three-dimensional coordinate information. A memory system that allows parallel accessing within a minimal amount of hardware is desirable in designing a VLSI processor. For this purpose, optimal memory allocation for parallel accessing designed for minimal memory capacity is important. In order to resolve the problem of increased search space for obtaining optimal allocation in global search, a method of limiting the search space by focusing on the periodicity of the three-dimensional coordinates of the memory module and the data stored in its is proposed. Evaluation of this VLSI processor reveals a significant reduction of the chip area under identical performance conditions.
|ジャーナル||Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)|
|出版ステータス||Published - 2004 6月|
ASJC Scopus subject areas
- コンピュータ ネットワークおよび通信