Triple-Stacked Silicon-on-Insulator Integrated Circuits Using Au/SiO2Hybrid Bonding

Yuki Honda; Masahide Goto; Toshihisa Watabe; Masakazu Nanba; Yoshinori Iguchi; Takuya Saraya; Masaharu Kobayashi; Eiji Higurashi; Hiroshi Toshiyoshi; Toshiro Hiramoto

doi:10.1109/S3S46989.2019.9320733

Triple-Stacked Silicon-on-Insulator Integrated Circuits Using Au/SiO₂Hybrid Bonding

Yuki Honda, Masahide Goto, Toshihisa Watabe, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

工学研究科・電子工学専攻

研究成果: 書籍の章/レポート/Proceedings › 会議への寄与 › 査読

1 被引用数 (Scopus)

抄録

This study demonstrates a triple-stacking process of a silicon-on-insulator (SOI) wafer by repeating (1) the embedment of 5-μm-diameter gold (Au) electrode sites in a polished silicon oxide (SiO2) surface, (2) Au/SiO2 hybrid bonding with a thin silicon layer in between, and (3) subsequent lost-wafer processes. Inverters prepared on separate SOI wafers are vertically connected through Au electrodes. Feasibility tests are performed by developing triple-stacked ring oscillators (ROs) with 101 stages. The experimental results confirm a successful RO operation and indicate that the developed process is promising for three-dimensional integrated circuits using the multi-wafer stacking technique.

本文言語	英語
ホスト出版物のタイトル	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
出版社	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子版）	9781728135236
DOI	https://doi.org/10.1109/S3S46989.2019.9320733
出版ステータス	出版済み - 2019 10月 14
イベント	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 - San Jose, 米国継続期間: 2019 10月 14 → 2019 10月 17

出版物シリーズ

名前	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019

会議

会議	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
国/地域	米国
City	San Jose
Period	19/10/14 → 19/10/17

文献へのアクセス

10.1109/S3S46989.2019.9320733

他のファイルとリンク

引用スタイル

Honda, Y., Goto, M., Watabe, T., Nanba, M., Iguchi, Y., Saraya, T., Kobayashi, M., Higurashi, E., Toshiyoshi, H., & Hiramoto, T. (2019). Triple-Stacked Silicon-on-Insulator Integrated Circuits Using Au/SiO₂Hybrid Bonding. In 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 記事 9320733 (2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S46989.2019.9320733

Honda, Yuki ; Goto, Masahide ; Watabe, Toshihisa その他. / Triple-Stacked Silicon-on-Insulator Integrated Circuits Using Au/SiO₂Hybrid Bonding. 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019).

@inproceedings{85963cb6bbcb4412af7b5a8c0d8b4747,

title = "Triple-Stacked Silicon-on-Insulator Integrated Circuits Using Au/SiO2Hybrid Bonding",

abstract = "This study demonstrates a triple-stacking process of a silicon-on-insulator (SOI) wafer by repeating (1) the embedment of 5-μm-diameter gold (Au) electrode sites in a polished silicon oxide (SiO2) surface, (2) Au/SiO2 hybrid bonding with a thin silicon layer in between, and (3) subsequent lost-wafer processes. Inverters prepared on separate SOI wafers are vertically connected through Au electrodes. Feasibility tests are performed by developing triple-stacked ring oscillators (ROs) with 101 stages. The experimental results confirm a successful RO operation and indicate that the developed process is promising for three-dimensional integrated circuits using the multi-wafer stacking technique.",

keywords = "3D integrated circuits (ICs), CMOS integrated circuits, integrated circuit interconnections, multi wafer stacking, silicon-on-insulator (SOI), wafer bonding",

author = "Yuki Honda and Masahide Goto and Toshihisa Watabe and Masakazu Nanba and Yoshinori Iguchi and Takuya Saraya and Masaharu Kobayashi and Eiji Higurashi and Hiroshi Toshiyoshi and Toshiro Hiramoto",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 ; Conference date: 14-10-2019 Through 17-10-2019",

year = "2019",

month = oct,

day = "14",

doi = "10.1109/S3S46989.2019.9320733",

language = "English",

series = "2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019",

address = "United States",

}

Honda, Y, Goto, M, Watabe, T, Nanba, M, Iguchi, Y, Saraya, T, Kobayashi, M, Higurashi, E, Toshiyoshi, H & Hiramoto, T 2019, Triple-Stacked Silicon-on-Insulator Integrated Circuits Using Au/SiO₂Hybrid Bonding. in 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019., 9320733, 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019, San Jose, 米国, 19/10/14. https://doi.org/10.1109/S3S46989.2019.9320733

Triple-Stacked Silicon-on-Insulator Integrated Circuits Using Au/SiO₂Hybrid Bonding. / Honda, Yuki; Goto, Masahide; Watabe, Toshihisa その他.
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 9320733 (2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019).

研究成果: 書籍の章/レポート/Proceedings › 会議への寄与 › 査読

TY - GEN

T1 - Triple-Stacked Silicon-on-Insulator Integrated Circuits Using Au/SiO2Hybrid Bonding

AU - Honda, Yuki

AU - Goto, Masahide

AU - Watabe, Toshihisa

AU - Nanba, Masakazu

AU - Iguchi, Yoshinori

AU - Saraya, Takuya

AU - Kobayashi, Masaharu

AU - Higurashi, Eiji

AU - Toshiyoshi, Hiroshi

AU - Hiramoto, Toshiro

PY - 2019/10/14

Y1 - 2019/10/14

N2 - This study demonstrates a triple-stacking process of a silicon-on-insulator (SOI) wafer by repeating (1) the embedment of 5-μm-diameter gold (Au) electrode sites in a polished silicon oxide (SiO2) surface, (2) Au/SiO2 hybrid bonding with a thin silicon layer in between, and (3) subsequent lost-wafer processes. Inverters prepared on separate SOI wafers are vertically connected through Au electrodes. Feasibility tests are performed by developing triple-stacked ring oscillators (ROs) with 101 stages. The experimental results confirm a successful RO operation and indicate that the developed process is promising for three-dimensional integrated circuits using the multi-wafer stacking technique.

AB - This study demonstrates a triple-stacking process of a silicon-on-insulator (SOI) wafer by repeating (1) the embedment of 5-μm-diameter gold (Au) electrode sites in a polished silicon oxide (SiO2) surface, (2) Au/SiO2 hybrid bonding with a thin silicon layer in between, and (3) subsequent lost-wafer processes. Inverters prepared on separate SOI wafers are vertically connected through Au electrodes. Feasibility tests are performed by developing triple-stacked ring oscillators (ROs) with 101 stages. The experimental results confirm a successful RO operation and indicate that the developed process is promising for three-dimensional integrated circuits using the multi-wafer stacking technique.

KW - 3D integrated circuits (ICs)

KW - CMOS integrated circuits

KW - integrated circuit interconnections

KW - multi wafer stacking

KW - silicon-on-insulator (SOI)

KW - wafer bonding

UR - https://www.scopus.com/pages/publications/85100843424

UR - https://www.scopus.com/inward/citedby.url?scp=85100843424&partnerID=8YFLogxK

U2 - 10.1109/S3S46989.2019.9320733

DO - 10.1109/S3S46989.2019.9320733

M3 - Conference contribution

AN - SCOPUS:85100843424

T3 - 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019

BT - 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019

Y2 - 14 October 2019 through 17 October 2019

ER -

Honda Y, Goto M, Watabe T, Nanba M, Iguchi Y, Saraya T その他. Triple-Stacked Silicon-on-Insulator Integrated Circuits Using Au/SiO₂Hybrid Bonding. In 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 9320733. (2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019). doi: 10.1109/S3S46989.2019.9320733