Ultra-fine-grain field-programmable VLSI using multiple-valued source-coupled logic

Haque Mohammad Munirul, Michitaka Kameyama

研究成果: Conference article査読

7 被引用数 (Scopus)


An ultra - fine - grain field - programmable VLSI processor using multiple-valued source-coupled logic called MV-FPVLSI is proposed for Implementing special purpose processors. To reduce the complexity of the interconnection blocks, a bit-serial pipeline architecture is employed. It also involves program-counter-less processor architecture based on direct allocation. The MV-FPVLSI consists of cells which are arranged in 2-D mesh array. Unlike a Field Programmable Gate Array (FPGA), data transmission occurs only between two adjacent cells and the overall data transmission delay is very small. Each cell consists of programmable multiple-valued-source coupled logic (MVSCL) circuits. Instead of using lookup tables, ultra-fine-grain logic operations can be done using MVSCL circuits. Moreover using the same hardware resources, each cell can be reconfigured to operate as one of a logic function, a memory function and a counter function. Additional versatility can be achieved through current- mode operation.

ジャーナルProceedings of The International Symposium on Multiple-Valued Logic
出版ステータスPublished - 2004 7月 26
イベントProceedings - 34th International Symposium on Multiple-Values Logic, ISMVL 2004 - Toronto, Ont, Canada
継続期間: 2004 5月 192004 5月 22

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)


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